Reconfigurable Memory Mapping for Neuromorphic Network Topologies
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Solution Overview
Problem
Current neuromorphic computers face inefficiencies in implementing various neural network topologies due to fixed memory mapping and interconnection schemes, leading to high overhead and energy consumption, especially when adapting to different neural network architectures.
Innovation Solution
A neuromorphic computer with reconfigurable memory mapping and interconnection networks that supports multiple neural network topologies, allowing for sparse and dense connections, both structured and pseudorandom, and enabling directed or undirected synaptic connections, thereby optimizing memory usage and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed memory mapping and interconnection schemes are used, then device complexity is reduced, but adaptability to different neural network topologies deteriorates
Solution Approach 1:
The patent implements dynamic memory mapping that can be reconfigured based on the specific neural network topology being executed. The system transitions from fixed to flexible addressing schemes, allowing the same hardware to adapt to different network architectures (feedforward, convolutional, recurrent, etc.) by changing memory access patterns and interconnection routes at runtime
Solution Approach 2:
The patent creates a universal neuromorphic processor that can implement multiple neural network topologies through a single reconfigurable memory system. The memory mapping engine provides multi-functionality by supporting various addressing modes (sparse, dense, structured, pseudorandom) and connection types (directed, undirected) within the same hardware framework
2Adaptability or versatility
If reconfigurable memory mapping is implemented, then adaptability to various neural network topologies is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into multiple independently configurable banks or regions, each capable of being mapped to different neural network components. This segmentation allows the complexity to be distributed and managed modularly, with each segment handling specific topology requirements without requiring complete system redesign
Solution Approach 2:
The patent introduces a memory mapping engine as an intermediary layer between the physical memory hardware and the neural network computation logic. This mediator handles the complexity of reconfiguration by translating high-level topology specifications into low-level memory access patterns, shielding the rest of the system from implementation details
3Device complexity
If fixed interconnection schemes are used, then device complexity is reduced, but energy efficiency for various neural network topologies deteriorates
Solution Approach 1:
The patent dynamically changes interconnection parameters (routing paths, memory access patterns, connection densities) based on the specific neural network topology being executed. For sparse connections, it uses compressed addressing; for dense connections, it employs broadcast mechanisms; for structured topologies, it utilizes regular patterns, thereby optimizing energy consumption for each case
4Quantity of substance
If storage overhead is reduced through reconfigurable mapping, then memory efficiency is improved, but access time for synapse weights may increase
Solution Approach 1:
The patent performs preliminary organization of synapse weights in memory based on the anticipated access patterns of the neural network topology. Before computation begins, the system pre-positions frequently accessed weights in optimized memory locations and establishes efficient access routes, reducing the need for complex runtime addressing and minimizing access delays
Data Source
AI summary
In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.