Neuromorphic Multi-Bit Processing with Reusable Axon and Synapse Circuits

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Solution Overview

Problem

Existing neuromorphic processors face inefficiencies in processing multi-bit operations due to limitations in handling multiple bits simultaneously, leading to suboptimal performance in neural network applications.

Innovation Solution

A neuromorphic apparatus and method that employs a single axon, synaptic, and neuron circuit, along with a controller, to process multi-bit operations through a time-division manner, where bits are sequentially assigned and combined to obtain a multi-bit neuromorphic operation result using a single adder.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single axon circuit, single synaptic circuit, and single neuron circuit are used to process multi-bit operations, then hardware complexity is reduced, but processing speed and productivity deteriorate due to sequential bit processing

Engineering Contradiction:
Improvehardware complexityVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent applies periodic action by dividing the multi-bit operation into sequential time periods, where each time period processes one bit combination. The controller periodically switches between different bit assignments (i-th bit and j-th bit) across multiple time periods, enabling a single circuit to handle multi-bit operations through time-division multiplexing.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements dynamics by making the circuit configuration adaptable over time. The controller dynamically reconfigures which bits are assigned to the single axon and synaptic circuits at different time periods, transforming a static single-bit circuit into a dynamic multi-bit processing system through temporal variation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple circuits are used to process multi-bit operations simultaneously, then processing speed is improved, but hardware complexity and resource requirements worsen

Engineering Contradiction:
Improveprocessing speedVSAvoidhardware requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a single axon circuit, single synaptic circuit, and single neuron circuit that can perform multiple functions by processing different bit combinations at different time periods. The same physical circuit is reused for multi-bit operations, eliminating the need for separate circuits for each bit position.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple bit processing functions into a single circuit system. By combining temporal processing of multiple bits through a single neuron circuit with sequential bit assignment controlled by a controller, the patent consolidates what would traditionally require multiple parallel circuits into one unified time-division system.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250322227A1Neuromorphic method and apparatus with multi-bit neuromorphic operation
Publication Date: 2025.10.16 SAMSUNG ELECTRONICS CO LTD
  • US20250322227A1 patent drawing
  • US20250322227A1 patent drawing
  • US20250322227A1 patent drawing

AI summary

A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.