Neuromorphic Multiplier Array Pulse-Width Modulation
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Solution Overview
Problem
Traditional CPUs are inadequate for processing-intensive tasks like machine learning, particularly deep learning, due to high power consumption, and existing neuromorphic chips face challenges in efficient synaptic weight programming and overshoot compensation.
Innovation Solution
A neuromorphic integrated circuit with a multiplier array that includes transistor-based cells for storing synaptic weights, capable of pulse-width modulation, and a charge integrator for integrating currents over input pulse widths, allowing for efficient digital routing between neural network layers and compensating for overshoot through re-programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional CPUs are used for machine learning processing, then processing capability can be maintained, but power consumption becomes excessively high
Solution Approach 1:
The patent replaces traditional digital signal processing with analog neuromorphic computing. Transistor-based cells perform multiplication operations through continuous current modulation rather than discrete digital logic, enabling energy-efficient processing of neural network computations. The analog nature of the system allows for low-power operation while maintaining processing capability for machine learning tasks.
Solution Approach 2:
The patent utilizes pulse-width modulation to encode information in the time domain, changing the state of transistor-based cells between conductive and non-conductive states. This parameter change enables the system to perform computational operations through temporal patterns of current flow, achieving both low power consumption and effective processing capability for neural network inference.
2Productivity
If neuromorphic chips are designed with high transistor count for enhanced processing capability, then processing capability improves, but power consumption increases
Solution Approach 1:
The patent implements periodic current pulses to activate transistor-based cells during specific computational cycles. By using periodic action rather than continuous operation, the system achieves effective processing capability while minimizing power consumption. The pulsed nature of current flow allows transistors to switch between active and idle states, reducing overall energy usage despite maintaining high processing capability through parallel operations.
3Measurement precision
If synaptic weights are programmed with high precision, then computational accuracy improves, but programming complexity and time increase
Solution Approach 1:
The patent employs a two-quadrant multiplier architecture where programming operations can overshoot the target synaptic weight value. By allowing excessive action during programming and then using compensation mechanisms, the system achieves sufficient precision without requiring complex step-by-step programming procedures. The overshoot compensation feature enables simpler programming operations while maintaining acceptable weight precision.
Solution Approach 2:
The patent incorporates feedback mechanisms in the two-quadrant multiplier to compensate for overshoot during synaptic weight programming. By monitoring the programming process and adjusting subsequent operations, the system achieves precise weight values through iterative refinement, reducing the complexity of the programming process while maintaining high precision.
4Measurement precision
If overshoot compensation is implemented in two-quadrant multipliers, then weight programming accuracy improves, but additional programming operations are required
Solution Approach 1:
The patent performs preliminary programming operations that intentionally overshoot the target synaptic weight value, then applies compensation operations to correct the overshoot. By preparing the system in advance with the overshoot condition and then applying a standardized compensation procedure, the system achieves high programming accuracy without requiring complex real-time adjustments, thereby minimizing the time penalty associated with compensation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables neuromorphic ICs to achieve significant power efficiency, reduce energy consumption, and streamline weight programming, making them suitable for battery-powered applications and improving processing capabilities for machine learning tasks.
Implementation Method 1
a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width
Data Source
AI summary
Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.