Neuromorphic Artificial Neuron Decoupling Read and Integration
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Solution Overview
Problem
Current neuromorphic chip implementations with resistive synapses face challenges such as low energy efficiency due to all-to-all connections, complex analogue integration of synaptic weights, and issues with RRAM memory reading, including parasitic writing and limited resistance range, which affect the accuracy and reliability of synaptic weight representation.
Innovation Solution
An artificial neuron design that includes a read circuit to impose a read voltage independent of the membrane voltage, providing an analogue value representative of the synaptic weight as duration, and a logic circuit to generate a pulse corresponding to this duration, allowing for decoupled reading and integration, thereby improving energy efficiency and reducing parasitic writing risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all-to-all connections are used in synaptic arrays, then connectivity between neurons is maximized, but energy consumption increases and efficiency decreases
Solution Approach 1:
The synaptic array is segmented into multiple banks, where each bank handles a subset of connections. This allows the system to achieve full connectivity across neurons while only activating the necessary segments for each computation, reducing overall energy consumption compared to maintaining all connections active simultaneously.
Solution Approach 2:
The system dynamically configures which synaptic connections are active based on computational needs. By selectively enabling only the required connections for each operation rather than maintaining all connections permanently active, the system achieves high adaptability while minimizing energy consumption.
2Measurement precision
If analogue integration of synaptic weights is implemented, then computational accuracy is improved, but circuit complexity and manufacturing difficulty increase
Solution Approach 1:
A current mirror circuit acts as an intermediary to transfer and replicate synaptic current signals without requiring complex analogue integration circuits. The current mirror provides accurate current replication that maintains computational precision while using a relatively simple circuit topology that is easier to manufacture.
Solution Approach 2:
The patent replaces complex analogue voltage integration with a current-based computational approach. By using current mirrors and current-mode logic, the system achieves analogue-like computational accuracy through current summation, which is more robust to manufacturing variations and requires simpler circuits than traditional voltage-based analogue integration.
3Quantity of substance
If RRAM memory is used for synapses, then density and non-volatility are improved, but parasitic writing occurs during reading operations
Solution Approach 1:
The read operation applies voltage locally and selectively to individual synapses through word lines and bit lines, rather than applying voltage globally across the entire memory array. This localized addressing ensures that only the targeted synapse is read while adjacent synapses remain unaffected, preventing parasitic writing in neighboring cells.
Solution Approach 2:
Access transistors serve as intermediaries between the read circuitry and the RRAM synapses. These transistors control and isolate the read current, ensuring that reading operations on one synapse do not inadvertently affect adjacent synapses, thereby preventing parasitic writing while maintaining high memory density.
4Ease of manufacture
If RRAM memory resistance range is limited, then manufacturing is simplified, but accuracy of synaptic weight representation deteriorates
Solution Approach 1:
The system compensates for the limited resistance range of RRAM devices by introducing a temporal dimension to weight representation. Instead of encoding weight magnitude solely through resistance values, the system uses the duration of synaptic current pulses to represent weight magnitude, allowing accurate weight representation despite constrained resistance ranges while maintaining manufacturing simplicity.
Solution Approach 2:
The patent changes the primary parameter for weight representation from resistance magnitude to pulse duration. By encoding synaptic weights in the time domain rather than the resistance domain, the system achieves high precision in weight representation while utilizing RRAM devices with limited resistance ranges, thus maintaining ease of manufacture without sacrificing accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances energy efficiency, reduces parasitic writing, and improves the accuracy of synaptic weight representation, enabling more reliable operation of neuromorphic chips by decoupling reading from integration and allowing for a broader voltage range, thus overcoming limitations in existing technologies.
Implementation Method 1
the conductance of which varies according to the voltage applied at their terminals... The variable resistance of these components can be increased (operation called Reset) or reduced (Set operation) if relatively high electric values (voltage and/or current) are applied thereto
Implementation Method 2
The imbalance of charges between the inside and the outside of the cell induces a voltage difference on either side of the membrane. This is called membrane voltage at the terminals of a membrane capacitance
Implementation Method 3
a 1T1R cell composed of a variable resistance M and of an access transistor T used to regulate the write currents
Data Source
AI summary
An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.