Configurable Neuromorphic Neuron Apparatus for Temporal Data Processing

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Solution Overview

Problem

Current neural network hardware systems lack efficient performance and flexibility in executing neural networks, particularly in handling temporal sequences and switching between different modes for various inference tasks.

Innovation Solution

An integrated circuit with a neuromorphic neuron apparatus that includes an input and an accumulation block with a state variable, allowing switching between two modes for performing inference tasks on temporal sequences, and utilizing memristive devices for efficient processing and memory storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If neural network hardware systems use conventional architecture, then manufacturing and operation are simpler, but performance and flexibility in handling temporal sequences are insufficient

Engineering Contradiction:
Improveperformance in handling temporal sequencesVSAvoidhardware architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The neuron apparatus is designed to be dynamically switchable between two operational modes: a first mode for processing temporal sequences using a state variable with decay function, and a second mode for non-temporal processing. This dynamic reconfigurability enables the hardware to adapt its computational behavior based on the input data characteristics, thereby improving productivity in handling temporal sequences without permanently increasing device complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The neuron apparatus incorporates a universal accumulation block that can perform multiple functions: it accumulates input signals over time using a decay function when processing temporal sequences, and processes immediate inputs when handling non-temporal data. This multi-functionality allows a single hardware unit to handle diverse neural network operations, improving temporal sequence processing performance while avoiding the need for separate specialized hardware for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If neural network hardware uses fixed mode operation, then device complexity is reduced, but adaptability to different inference tasks is limited

Engineering Contradiction:
Improveflexibility in switching between inference tasksVSAvoidmode switching mechanism complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The neuron apparatus includes a mode selection mechanism that enables dynamic switching between first mode (temporal sequence processing with state variable) and second mode (immediate processing without state dependency). This dynamic mode switching capability provides adaptability to different inference tasks while maintaining relatively simple device complexity through shared hardware resources that operate differently based on the selected mode.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The apparatus changes its operational parameters by switching between modes: in the first mode, the accumulation block uses a decay function and maintains state variables for temporal processing, while in the second mode, it processes inputs immediately without state persistence. This parameter change approach enables versatility in handling different inference tasks by adjusting the computational behavior rather than requiring completely different hardware configurations.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If conventional neural network hardware is used, then energy consumption may be lower for simple tasks, but processing efficiency for temporal data is insufficient

Engineering Contradiction:
Improveprocessing efficiency of temporal dataVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The invention merges the accumulation function with the neuron processing unit, creating an integrated accumulation block within the neuron apparatus. This consolidation allows temporal sequence processing and immediate processing to occur within a single unified hardware structure, improving processing efficiency for temporal data while managing energy consumption by avoiding the need for separate processing units that would increase overall system energy requirements.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The accumulation block automatically manages state variables and decay functions for temporal processing without requiring external control intervention. The state variable is updated and maintained autonomously based on incoming inputs and the configured decay function, enabling efficient temporal data processing while minimizing the energy overhead associated with external control mechanisms.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20220138540A1Integrated circuit with a configurable neuromorphic neuron apparatus for artificial neural networks
Publication Date: 2022.05.05 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20220138540A1 patent drawing
  • US20220138540A1 patent drawing
  • US20220138540A1 patent drawing

AI summary

The present disclosure relates to an integrated circuit comprising a first neuromorphic neuron apparatus. The first neuromorphic neuron apparatus comprises an input and an accumulation block having a state variable for performing an inference task on the basis of input data comprising a temporal sequence. The first neuromorphic neuron apparatus may be switchable in a first mode and in a second mode. The accumulation block may be configured to perform an adjustment of the state variable using a current input signal of the first neuromorphic neuron apparatus and a decay function indicative of a decay behavior of the apparatus. The state variable may be dependent on previously received one or more input signals of the first neuromorphic neuron apparatus.