Neuromorphic Network-on-Chip for Sparse Connectivity

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Solution Overview

Problem

Traditional neuromorphic computers face limitations in implementing large-scale neural networks due to interconnect bottlenecks, area, and power overheads, particularly in achieving sparse and reconfigurable connectivity and online learning, which are essential for mimicking biological neural networks.

Innovation Solution

A neural network with reconfigurable sparse/dense connectivity and online learning is implemented using a Network-on-Chip (NoC) architecture, where neuromorphic cores and synapse cores are tiled and grouped to share routers, enabling flexible connectivity and online spike-timing dependent plasticity (STDP) learning, with dynamic address generation and wildcard masked multicasting to optimize memory usage and power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional neuromorphic computers implement large-scale neural networks with sparse and reconfigurable connectivity, then the network's ability to mimic biological neural networks and perform online learning is improved, but interconnect bottlenecks, area overhead, and power consumption increase

Engineering Contradiction:

Improvesparse and reconfigurable connectivityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The system is divided into multiple neuromorphic cores, each handling a subset of neurons and synapses. Each core has local interconnect resources, and a network-on-chip (NoC) provides global connectivity. This segmentation allows the system to achieve large-scale sparse connectivity without requiring a fully interconnected architecture, thereby reducing power consumption and area overhead while maintaining reconfigurability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical interconnect architecture with multiple dimensions: local interconnect within cores, regional interconnect through router groups, and global interconnect via the NoC. This multi-dimensional approach enables efficient routing of spike messages across the network, reducing the burden on any single interconnect layer and enabling sparse connectivity patterns that mimic biological neural networks.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

Engineering Contradiction:

Improvesparse and reconfigurable connectivityVSAvoidarea overhead

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Multiple neuromorphic cores share common NoC infrastructure and router groups, merging interconnect resources to serve multiple computational units. This sharing approach reduces the total area required for interconnect resources compared to providing dedicated interconnect for each core, while still enabling reconfigurable connectivity patterns across the entire network.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The NoC and router infrastructure is designed to be universal, serving multiple neuromorphic cores and supporting various connectivity patterns (sparse, dense, reconfigurable) through software configuration rather than hardware specialization. This multi-functionality reduces area overhead by avoiding dedicated hardware for each connectivity type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If neuromorphic cores and synapse cores are tiled and grouped to share routers, then memory usage and power consumption are reduced, but the complexity of address generation and routing increases

Engineering Contradiction:

Improvepower consumptionVSAvoidaddress generation and routing complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent replaces complex hardware-based address generation and routing decision logic with software-based control. A configuration memory stores routing tables and address mapping information that can be programmatically adjusted. This substitution reduces hardware complexity and power consumption while maintaining flexible routing capabilities through software-configurable address generation.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Quantity of substance

If wildcard masked multicasting is used to optimize memory usage, then memory efficiency is improved, but the complexity of routing logic increases

Engineering Contradiction:

Improvememory usage efficiencyVSAvoidrouting logic complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

Complex wildcard masking and multicasting logic is implemented through software configuration rather than hardwired hardware logic. The routing tables in configuration memory encode the wildcard masking rules and multicasting behavior, allowing memory-efficient address generation without requiring complex combinatorial logic circuits. This approach reduces hardware complexity while maintaining memory usage efficiency.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10713558B2Neural network with reconfigurable sparse connectivity and online learning

Publication Date: 2020.07.14 INTEL CORP

AI summary

In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.