Free-Running Neuromorphic Processor Eliminates Spike Buffers
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Solution Overview
Problem
Existing neuromorphic computers are inefficient in terms of area and power due to the need for large spike buffers to store incoming spikes, and require global synchronization signals for time-step updates, which adds significant routing and power overheads.
Innovation Solution
A scalable, free-running neuromorphic processor design that uses pseudo-random number generators to control spiking activity and integrate spikes between inter-spike intervals, eliminating the need for spike buffers and global synchronization signals by enabling event-driven communication and local time-step updates within each core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spike buffers are used to store incoming spikes in existing neuromorphic computers, then spike integration can be performed, but area and power consumption increase significantly
Solution Approach 1:
The patent removes the spike buffer component entirely from the system. Instead of storing spikes in buffers, the system integrates spikes directly as they arrive at the neuromorphic core, extracting the buffering function and replacing it with event-driven direct integration logic.
Solution Approach 2:
The system performs preliminary action by pre-configuring the neuromorphic core with the ability to integrate spikes directly upon arrival. The core is designed with integrated spike processing logic that is ready to handle incoming spikes without requiring intermediate storage, enabling immediate integration when spikes arrive.
2Reliability
If global synchronization signals are used for time-step updates in existing neuromorphic computers, then neurons can be updated across the system, but routing overhead and power consumption increase significantly
Solution Approach 1:
The patent segments the synchronization function from a global system-level operation to a local core-level operation. Each neuromorphic core maintains its own time-step state independently, eliminating the need for global synchronization signals. The system divides the synchronization task into independent local units that operate autonomously.
Solution Approach 2:
Each neuromorphic core serves itself by maintaining its own time-step counter and state independently. The core automatically advances its own time-step without requiring external synchronization signals from other cores or a central controller, enabling self-synchronized operation across the system.
3Reliability
If spike buffers with depth sufficient for axonal delays are used, then spikes can be stored during transmission delays, but area and power overhead increase
Solution Approach 1:
The patent removes the spike buffer that was previously used to hold spikes during axonal transmission delays. Instead of buffering spikes to compensate for transmission time, the system processes spikes as they arrive and uses event-driven timing mechanisms to handle the temporal aspects of spike transmission without requiring deep buffers.
4Reliability
If deep spike buffers are used to address axonal delays, then spikes can be integrated after transmission, but area overhead increases significantly
Solution Approach 1:
The system performs preliminary action by pre-configuring the neuromorphic core with integrated spike processing capability. The core is designed to handle spike integration immediately upon arrival, with pre-established logic for timing and integration, eliminating the need for deep buffers to hold spikes during transmission delays.
Data Source
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AI summary
Apparatus and method for a scalable, free running neuromorphic processor. For example, one embodiment of a neuromorphic processing apparatus comprises: a plurality of neurons; an interconnection network to communicatively couple at least a subset of the plurality of neurons; a spike controller to stochastically generate a trigger signal, the trigger signal to cause a selected neuron to perform a thresholding operation to determine whether to issue a spike signal.