Neuromorphic Memory Device Series Parallel Resistive Configuration
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Solution Overview
Problem
Conventional memory devices used in neuromorphic computing suffer from write-errors, endurance issues, high error rates, high writing energy, and low sensing margin, making them unsuitable for efficient neural computations due to their binary nature, which differs significantly from the analog multi-level synaptic connections in the brain.
Innovation Solution
The neuromorphic memory device employs a series and parallel configuration of resistive storage elements, coupled with logic and transistors, allowing multiple resistance states based on data storage, enabling efficient neural computations by mimicking brain-like synaptic connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional binary memory devices are used, then device complexity is reduced, but analog multi-level synaptic capabilities are lost
Solution Approach 1:
The memory device is segmented into two separate resistive storage elements (first and second resistive storage elements) that can be independently configured. Each element can operate in series or parallel arrangements, creating multiple resistance states without requiring a single complex multi-level cell. This segmentation enables analog-like behavior through simple binary elements.
Solution Approach 2:
The same two resistive storage elements serve multiple functions: they can be configured in series or parallel arrangements to create different resistance states, enabling both digital storage and analog computing modes. The logic circuit dynamically reconfigures the arrangement based on operational mode, making the device universal for both digital and neuromorphic applications.
2Adaptability or versatility
If analog storage devices are used, then synaptic computing capabilities are improved, but write-errors and endurance issues increase
Solution Approach 1:
The device dynamically switches between series and parallel configurations of the resistive storage elements based on the operational mode (digital or neuromorphic). This dynamic reconfiguration allows the system to optimize for reliability in digital mode and for synaptic capabilities in analog mode, avoiding the trade-off by adapting the circuit topology rather than relying on a single analog storage mechanism.
Solution Approach 2:
The logic circuit acts as an intermediary that controls the configuration of the resistive storage elements. It receives operation mode signals and appropriately connects the storage elements in series or parallel arrangements, enabling the system to switch between reliable digital operation and analog synaptic computation without direct interference between the two modes.
3Measurement precision
If conventional memory devices are used, then manufacturing simplicity is maintained, but sensing margin between states is reduced
Solution Approach 1:
By segmenting the memory into two separate resistive storage elements with distinct resistance states each, the device creates multiple well-separated resistance levels when combined in series or parallel. This segmentation naturally increases the sensing margin between different memory states compared to a single multi-level cell, while maintaining compatibility with standard resistive memory fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides robust digital storage with analog computing capabilities, offering a good sense margin between states, enabling fast SRAM digital memory, low-power NVM digital memory, and analog neuromorphic memory modes, acting as an on-demand accelerator for neural computing.
Implementation Method 1
a first resistive storage element; a second resistive storage element
Implementation Method 2
a first routing transistor having a first source/drain coupled to the first resistive storage element, a second source/drain coupled to the first source line, and a gate coupled to the memory cell
Data Source
AI summary
One illustrative device includes, among other things, a first resistive storage element; a second resistive storage element; and logic to couple the first resistive storage element and the second resistive storage element in a series arrangement in a first configuration and to couple the first resistive storage element and the second resistive storage element in a parallel arrangement in a second configuration.