Low Spike Count Ring Buffer on Neuromorphic Hardware
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Solution Overview
Problem
Existing neuromorphic systems face inefficiencies due to high spike counts when implementing ring buffers, which degrade system performance and increase power consumption, especially in multichip systems, and require either stochastic neurons that add noise or create a large number of unnecessary spikes.
Innovation Solution
A low-spike-count ring-buffer mechanism is implemented on neuromorphic hardware, allowing for configurable runtime settings such as memory cell count, tick retention, and output frequency, using a demultiplexer to write spikes sequentially to memory cells and output based on subsets, reducing unnecessary spike production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional ring buffer implementation is used on neuromorphic hardware, then the buffer can store and retrieve spike data, but the spike count becomes excessively high which degrades system performance and increases power consumption
Solution Approach 1:
The ring buffer is segmented into multiple memory cells organized in a circular structure, where each cell stores a portion of the spike data. This segmentation allows the system to process and retrieve data in manageable chunks rather than handling all spikes uniformly, thereby reducing the effective spike count processed at any given time while maintaining buffer functionality.
Solution Approach 2:
The ring buffer implements periodic writing and reading operations at designated access points in the circular memory structure. By periodically accessing specific memory cells rather than continuously processing all spikes, the system reduces the instantaneous spike count handled, improving performance and reducing power consumption while maintaining data retention over the specified tick duration.
2Adaptability or versatility
If stochastic neurons are used to implement ring buffer, then the buffer functionality is achieved, but noise is introduced into the system
Solution Approach 1:
The patent introduces dedicated memory cells as intermediary storage elements between the spike input and processing units. These memory cells act as a buffer that deterministically stores spike data without requiring stochastic neurons, thereby eliminating the noise generation associated with stochastic implementations while maintaining the ring buffer's adaptability and functionality.
3Reliability
If high spike count is used in multichip systems, then the ring buffer can maintain data, but power consumption increases significantly
Solution Approach 1:
The ring buffer implementation uses local memory cells with specific retention properties tailored to their position in the circular buffer. Each memory cell is configured to retain data for the required tick duration without requiring excessive spikes, and the demultiplexer directs spikes to appropriate local memory cells, reducing overall power consumption while maintaining data retention reliability across the multichip system.
4Adaptability or versatility
If configurable runtime settings are implemented, then the system becomes more adaptable to different requirements, but device complexity increases
Solution Approach 1:
The ring buffer is designed with universal control mechanisms that handle multiple configuration parameters (buffer size, tick retention, output frequency) through a unified demultiplexer and memory cell structure. This universal design allows the same hardware structure to adapt to different runtime requirements without requiring separate specialized circuits for each parameter, thereby reducing overall device complexity while maintaining high adaptability.
Data Source
AI summary
Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.