Neuromorphic Circuit Scalability via Local Spike Timing

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Solution Overview

Problem

The scalability of neuromorphic computing hardware is limited by constraints such as the maximum spike number per neuron, buffer size, and on-chip memory, which hinder the increase in hardware scale and efficiency in machine learning and reasoning tasks.

Innovation Solution

A neuromorphic computing circuit configuration that omits the use of global counters, employing a time-difference calculation circuit array and routers to calculate time differences without physical distance considerations, allowing for increased scalability and efficient spike transmission and connection strength updates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If global counters are used to track spike timing, then time difference calculation is enabled, but hardware scalability is limited by buffer size and maximum spike number constraints

Engineering Contradiction:
Improvetime difference calculation precisionVSAvoidhardware scalability
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the global counter mechanism from the system and replaces it with local counter implementations at each node. Each node maintains its own counter to track spike timing, eliminating the need for a centralized global counter and its associated buffer constraints. This extraction enables independent operation of each node while maintaining time difference calculation capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the centralized time tracking function into distributed local counters at each node. Instead of one global counter serving all nodes, each node has its own counter that independently tracks spike timing events. This segmentation removes the single point of constraint (global buffer size) and allows parallel scaling across multiple nodes.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If buffer size is increased to handle more spikes, then more spikes can be processed, but hardware scale and complexity increase

Engineering Contradiction:
Improvenumber of spikes processedVSAvoidhardware scale
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Each node serves itself by maintaining local counters and tracking its own spike timing events independently. Nodes do not rely on a centralized buffer to store spike timing information,而是 using their own local resources. This self-service approach eliminates the need for large shared buffers and enables linear scaling with node count.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent segments the spike processing function so that each node independently handles its own spike timing tracking. The total spike processing capacity scales with the number of nodes rather than being limited by a single buffer size, achieving parallel processing without centralized bottlenecks.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If connection strength accumulation is performed for all received spikes, then learning accuracy improves, but computational load and energy consumption increase

Engineering Contradiction:
Improvelearning accuracyVSAvoidcomputational energy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent introduces a threshold parameter for connection strength accumulation. Instead of accumulating connection strengths for all spikes, the system only accumulates when the time difference falls within a specified threshold range. This parameter-based filtering reduces the number of accumulation operations while preserving the most relevant spikes for learning, thereby reducing energy consumption.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies partial action by selectively accumulating connection strengths only for spikes that meet the time difference criterion, rather than accumulating for all spikes. This partial accumulation approach maintains learning accuracy for relevant spikes while avoiding unnecessary computational energy expenditure on irrelevant spikes.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250094794A1Neuromorphic computing circuit and method for control
Publication Date: 2025.03.20 FUJITSU LTD
  • US20250094794A1 patent drawing
  • US20250094794A1 patent drawing
  • US20250094794A1 patent drawing

AI summary

A neuromorphic computing circuit includes nodes including first and second nodes generating a spike including a counter for a spike existing time and a sender information, and a transmission array including transmission circuits, one or more of which is on the transmission path and forwards the spike. Each transmission circuit updates a counter value when forwarding the spike and sets, when detecting meeting of a first spike from the first to the second node and a second spike from the second to the first node, time difference based on the counter values, into the first spike. The second node includes a generation circuit specifying time difference equal or less than a first threshold among ones in the received spikes, accumulating connection strengths between the sender of third spikes set the specified differences therein and the second node, and generating a fourth spike when the accumulating result exceeds a second threshold.