Neuromorphic Synapse Array Using FeFETs for Excitatory and Inhibitory Operations
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Solution Overview
Problem
Current neuromorphic devices face challenges in efficiently mimicking the excitatory and inhibitory synapse operations of the human brain, particularly in varying synapse weights to modulate current flow effectively, which is crucial for learning and pattern recognition processes.
Innovation Solution
The implementation of a synapse array in neuromorphic devices using n-type and p-type ferroelectric field effect transistors (FeFETs) and resistive elements, where the synapses can perform both excitatory and inhibitory operations by varying the polarization voltages and read voltages applied to the transistors, allowing for controlled current flow through the resistive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional neuromorphic devices are used, then basic synapse operations can be performed, but the ability to efficiently vary synapse weights and modulate current flow is insufficient
Solution Approach 1:
The patent employs n-type and p-type FeFETs whose channel conductivity can be dynamically adjusted through polarization voltage application. The ferroelectric material in the gate allows the transistor to switch between different conductivity states, enabling dynamic synapse weight variation and effective current flow modulation that mimics biological synapse plasticity.
Solution Approach 2:
The patent changes the electrical parameters (polarization voltage, read voltage) of the FeFETs to control synapse weights. By applying different voltage polarities and magnitudes to the n-type and p-type FeFETs, the device can vary its conductance state continuously, achieving efficient current flow modulation for learning and pattern recognition processes.
2Adaptability or versatility
If separate excitatory and inhibitory synapse circuits are implemented, then distinct operations can be performed, but device complexity and power consumption increase
Solution Approach 1:
The patent implements a universal synapse circuit that can perform both excitatory and inhibitory operations using a single integrated structure. The n-type and p-type FeFETs share common source and drain electrodes, allowing the same physical circuit to exhibit different operational modes (excitatory or inhibitory) by controlling the polarization states of the ferroelectric materials, thereby reducing device complexity while maintaining functional versatility.
Solution Approach 2:
The patent merges the excitatory and inhibitory synapse functions into a single integrated circuit unit. The n-type FeFET and p-type FeFET are combined with shared resistive elements and electrodes, creating a unified structure that can perform both types of synapse operations through coordinated control of the two transistor types, thus simplifying the overall device architecture.
3Area of stationary object
If integrated synapse array is implemented, then area efficiency is improved, but power consumption increases
Solution Approach 1:
The patent utilizes periodic voltage application to the FeFET gates to achieve synapse weight updates only when needed. The ferroelectric material retains its polarization state between updates, allowing the device to maintain synapse weights without continuous power supply. This periodic actuation reduces power consumption while maintaining the integrated array structure.
Solution Approach 2:
The patent applies local quality by enabling selective operation of individual synapses or subsets of synapses within the integrated array. By applying voltages only to specific row lines or column lines, the device can update or read specific synapse weights without activating the entire array, thereby reducing overall power consumption while maintaining area efficiency through integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the neuromorphic device to effectively modulate current flow based on synapse weights, enhancing learning and pattern recognition capabilities by allowing both excitatory and inhibitory operations, thereby improving the integration and reducing power consumption.
Implementation Method 1
n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a gate electrode and a body; a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a gate electrode and a body
Data Source
AI summary
A synapse array of a neuromorphic device is provided. The synapse array may include a pre-synaptic neuron; a row line extending from the pre-synaptic neuron in a row direction; a post synaptic neuron; a column line extending from the post-synaptic neuron in a column direction; and a synapse disposed at an intersection region between the row line and the column line. The synapse may include an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a gate electrode and a body; a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a gate electrode and a body; and a resistive element having a first node electrically connected to the source electrode of the n-FeFET and electrically connected to the source electrode of the p-FeFET, and the n-FeFET and the p-FeFET are electrically connected in series.