Neuromorphic Synapse Gate Stack Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional neuromorphic computing systems face challenges with low linearity and high operating voltage in synapse devices, particularly in floating gate memory-based systems, which hinder efficient and low-power data processing and storage.
Innovation Solution
A FET-based neuromorphic synapse device is developed with a modified gate stack structure, incorporating a control gate region and a charge transfer layer to enhance linearity and symmetry in weight potentiation and depression characteristics, while maintaining the technical maturity of floating gate memory technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional floating gate memory device is used as a synapse device, then the device can be manufactured with mature technology, but the linearity and symmetry of weight update characteristics are poor and the operating voltage is high
Solution Approach 1:
The gate structure is segmented into multiple functional regions: a first gate electrode for controlling charge injection into the floating gate, a second gate electrode for controlling charge extraction from the floating gate, and the floating gate itself. This segmentation allows independent optimization of potentiation and depression operations, improving linearity and symmetry of weight updates while maintaining manufacturing maturity
Solution Approach 2:
The charge transfer layer is introduced as an intermediary between the floating gate and the gate electrodes. This layer mediates the charge transfer process, enabling precise control over charge injection and extraction. The charge transfer layer improves the linearity of weight updates by providing a controlled interface for charge movement, while allowing the use of mature floating gate manufacturing processes
2Device complexity
If a conventional floating gate memory device is used as a synapse device, then the device structure is simple, but the operating voltage is high which increases energy consumption
Solution Approach 1:
The invention changes the electrical parameters of the gate structure by introducing a charge transfer layer with specific material properties and thickness. This layer enables efficient charge transfer at lower voltages, reducing the operating voltage from conventional high levels to below 5V. The parameter changes in the gate structure maintain relative simplicity while achieving significant energy reduction through improved charge control efficiency
3Reliability
If additional selector devices are added to improve synapse device functionality, then the device performance is enhanced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The multi-electrode gate structure performs multiple functions within a single device architecture: the first gate electrode controls charge injection for potentiation, the second gate electrode controls charge extraction for depression, and the floating gate stores the weight information. This multi-functionality eliminates the need for separate selector devices, reducing overall device complexity while enhancing synapse functionality and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high linearity and symmetry in weight updates with reduced operating voltage, enabling efficient and low-power neuromorphic computing by modifying the gate stack structure of conventional floating gate memory-based synapse devices.
Implementation Method 1
a control gate region (150), which is formed on the charge transfer layer region and which generates a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied
Data Source
AI summary
Disclosed are a neuromorphic synapse device having an excellent linearity characteristic, and an operating method thereof. According to an embodiment, a neuromorphic synapse device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a charge transfer layer region formed on the floating gate region, and a control gate region, which is formed on the charge transfer layer region and which generates a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied, and performs a weight update operation by releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region by using the potential difference.