3D Stacked Neuromorphic Synapse Device Using Schottky Barrier Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Neuromorphic computing systems face limitations in power consumption and signal delay due to complex connections between synapse and neuron devices, which are exacerbated by the need for ion implantation and high-temperature heat treatment processes in conventional synapse devices.
Innovation Solution
A neuromorphic device with a three-dimensional stacked structure using a Schottky barrier transistor that eliminates the need for ion implantation and high-temperature heat treatment, featuring a synapse device with metal silicide source/drain and a floating gate, connected via vertical wiring to minimize interconnecting length and improve integration, power efficiency, and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synapse devices using ion implantation and high-temperature heat treatment are used, then synaptic operation characteristics can be achieved, but device complexity and manufacturing difficulty increase due to the need for additional process steps
Solution Approach 1:
The patent extracts and eliminates the ion implantation and high-temperature heat treatment processes from the synapse device fabrication. By using a Schottky barrier transistor structure with metal silicide source/drain, the invention removes these complex additional process steps while maintaining synaptic operation characteristics through the floating gate mechanism alone.
Solution Approach 2:
The patent changes the material parameter of the source/drain from conventional doped semiconductor to metal silicide, which forms a Schottky junction with the channel. This parameter change eliminates the need for ion implantation and high-temperature annealing processes, simplifying the manufacturing while preserving synaptic functionality.
2Productivity
If three-dimensional stacked structure is implemented, then integration density and speed improve by reducing interconnecting length, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar two-dimensional layout to three-dimensional stacked structure, placing the synapse device vertically above the neuron device. This dimensional change reduces the horizontal interconnecting length and increases integration density, with the floating gate extending laterally to provide sufficient overlap for synaptic operation.
3Loss of time
If vertical connection wiring is used to connect lower device and synapse device, then signal delay and power consumption decrease due to reduced interconnecting length, but manufacturing complexity increases
Solution Approach 1:
The patent merges the vertical connection wiring with the floating gate structure of the synapse device. The floating gate serves dual purposes: as the synaptic weight storage element and as the lateral connection that extends to overlap with the channel, thereby providing both the vertical interconnection and the synaptic function in a unified structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of neuromorphic devices with enhanced integration, power efficiency, and speed by eliminating the need for high-temperature processes, reducing interconnecting length and improving synaptic operation characteristics.
Implementation Method 1
a source/drain having a metal silicide forming a Schottky junction with the channel
Data Source
AI summary
A neuromorphic devices may be formed having a three-dimensional stacked structure. The neuromorphic device may include a lower device formed on a substrate, an interlayer insulating layer formed on the substrate to cover the lower device, a synapse device having a Schottky barrier transistor structure formed on the interlayer insulating layer, and a vertical connection wiring formed in the interlayer insulating layer to electrically connect the lower device and the synapse device. The synapse device may include a channel, a source having a metal silicide forming a first Schottky junction with the channel, a drain having a metal silicide forming a second Schottky junction with the channel, a floating gate for a synaptic operation, and a control gate. The synapse device may be formed using only low-temperature processes performed at less than about 500° C.