Neuromorphic Synapse Element With Segmented Bit Cells
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Solution Overview
Problem
Current neuromorphic processors face challenges with excessive power consumption and a narrow dynamic range of output, limiting their applicability to real-world applications.
Innovation Solution
A neuromorphic processor design incorporating a synapse element with a configuration of first and second bit cells connected to wordlines and inverted wordlines, utilizing variable resistance memory elements and transistors to perform calculations and store synapse values, allowing for extended dynamic range and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional neuromorphic processor designs are used, then the device can perform basic machine learning operations, but power consumption is excessive and dynamic range is narrow
Solution Approach 1:
The synapse element is divided into two separate bit cells (first bit cell and second bit cell) instead of using a single bit cell. Each bit cell independently stores one bit of synapse data and performs calculations, allowing the system to achieve both low power consumption and extended dynamic range through coordinated operation of the segmented cells
Solution Approach 2:
The patent introduces inverted wordlines and inverted bitlines to create additional operational dimensions. By applying voltages to these inverted lines in complementary patterns, the system extends the dynamic range beyond what a conventional single-bit cell architecture can provide, while maintaining low power consumption through selective activation
2Device complexity
If a single bit cell is used per synapse element, then the device structure is simpler, but the dynamic range of output is narrow
Solution Approach 1:
The synapse element is divided into two separate bit cells (first bit cell and second bit cell) instead of using a single bit cell. Each bit cell independently stores one bit of synapse data and performs calculations, allowing the system to achieve both low power consumption and extended dynamic range through coordinated operation of the segmented cells
Solution Approach 2:
The patent introduces inverted wordlines and inverted bitlines to create additional operational dimensions. By applying voltages to these inverted lines in complementary patterns, the system extends the dynamic range beyond what a conventional single-bit cell architecture can provide, while maintaining low power consumption through selective activation
3Adaptability or versatility
If multiple bit cells are used per synapse element, then the dynamic range is extended, but power consumption increases
Solution Approach 1:
The synapse element is divided into two separate bit cells (first bit cell and second bit cell) instead of using a single bit cell. Each bit cell independently stores one bit of synapse data and performs calculations, allowing the system to achieve both low power consumption and extended dynamic range through coordinated operation of the segmented cells
Solution Approach 2:
The patent employs periodic switching of voltage applications to the first and second bit cells through complementary wordline and inverted wordline activations. This periodic action allows the multiple bit cells to operate in an energy-efficient manner by activating only the necessary cells at each time step, thereby extending dynamic range while controlling power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a neuromorphic processor with improved dynamic range and reduced power consumption, facilitating more efficient and effective machine learning operations.
Implementation Method 1
a first variable resistance memory element connected in series with a first transistor between a first input node and a first output node
Implementation Method 2
a first transistor connected in series with the first variable resistance memory element
Implementation Method 3
perform a calculation operation using the first input and the first synapse value, and output a result of the calculation
Data Source
AI summary
A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.