Neuromorphic Synapse Transistor Leakage Current Control
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Solution Overview
Problem
Current neuromorphic devices face challenges in achieving high accuracy for learning and recognition due to leakage currents, which increase the likelihood of learning errors as the number of trained column lines and row lines increases, and integrating transistors without occupying large areas is difficult.
Innovation Solution
A neuromorphic device design that incorporates transistors with floating gates and control gates at synapse intersections, where the transistors have a 1-transistor structure with a floating gate and a control gate insulated from it, reducing threshold voltage and preventing leakage currents by turning off transistors coupled to previously trained row lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors are integrated at synapse intersections to enable learning and recognition, then device functionality is improved, but leakage currents increase causing learning errors
Solution Approach 1:
The patent extracts and eliminates the harmful leakage current component by introducing a blocking mechanism. Specifically, it uses a second transistor configured to block leakage currents from previously trained row lines, effectively removing the harmful factor while preserving the useful learning functionality of the synapse circuits.
Solution Approach 2:
The patent introduces an intermediary blocking transistor that mediates between the trained row lines and the currently active synapses. This intermediary component prevents harmful leakage currents from interfering with active learning operations, thereby maintaining reliability without sacrificing functionality.
2Productivity
If more row lines and column lines are added to increase processing capacity, then productivity is improved, but leakage currents increase causing more learning errors
Solution Approach 1:
The patent segments the control of each row line by introducing individual blocking transistors for each row. This segmentation allows independent control of leakage current blocking for each row, enabling the system to scale to more row lines and column lines while maintaining learning accuracy through targeted leakage suppression.
3Area of stationary object
If transistor size is reduced to increase integration density, then area efficiency is improved, but threshold voltage control becomes difficult
Solution Approach 1:
The patent employs asymmetric transistor sizing where the blocking transistors are optimized independently from the synapse transistors. The blocking transistors can be larger to ensure reliable leakage blocking, while the synapse transistors can be smaller for high integration density. This asymmetric design allows each transistor type to be optimized for its specific function without compromising overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the integration density and reduces learning errors by blocking leakage currents, thereby improving the accuracy of learning and recognition processes in neuromorphic devices.
Implementation Method 1
A threshold voltage of the transistor decreases when a certain charge is trapped in the floating gate
Implementation Method 2
a tunnel insulating layer, a floating gate, and a charge blocking layer sequentially encircling the semiconductor pillar, the tunnel insulating layer being disposed against a side surface of the semiconductor pillar
Data Source
AI summary
A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first direction; a plurality of column lines extending in a second direction that crosses the first direction; and a plurality of synapses positioned at intersections of the row lines, the additional row lines, and the column lines, wherein each of the synapses includes a transistor comprising a floating gate, a control gate insulated from the floating gate, a first junction, and a second junction, the control gate being coupled to a corresponding one of the plurality of row lines, the first junction being coupled to a corresponding one of the plurality of additional row lines, the second junction being coupled to a corresponding one of the plurality of column lines.