Neuromorphic Synapse With Transistor and Memristor for Conductance Modulation
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Solution Overview
Problem
Conventional neuromorphic synaptic devices face challenges in achieving a trade-off between symmetry and linearity of conductance modulation, leading to issues such as sneak path problems and inefficient pattern recognition, especially when implemented in crossbar array structures.
Innovation Solution
A neuromorphic device design incorporating a transistor and two-terminal variable resistance memory devices, where a separate memory voltage is applied to each device to control the gate voltage, allowing for modulated conductance and preventing sneak paths by adjusting the conductance of each memristor device independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional memristor-based synaptic devices are used for conductance modulation, then the device structure remains simple, but the trade-off between symmetry and linearity of conductance modulation cannot be resolved
Solution Approach 1:
The synaptic device is segmented into multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) with distinct functions. The first and second conductive layers control symmetry through separate voltage applications, while the third conductive layer manages linearity. This segmentation allows independent optimization of symmetry and linearity without compromising device structural simplicity.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first and second conductive layers. This insulating layer enables independent voltage control of the first and second conductive layers, allowing separate adjustment of symmetry and linearity parameters. The intermediary structure resolves the trade-off by providing electrical isolation while maintaining functional integration.
2Productivity
If crossbar array structures are used for neuromorphic systems, then integration density increases, but sneak path problems occur
Solution Approach 1:
The synaptic device implements local quality control by assigning different functional characteristics to different conductive layers. The first conductive layer optimizes for symmetry, the second for linearity, and the third for sneak path suppression. This localized functional differentiation allows the crossbar array to maintain high integration density while each device independently suppresses sneak paths through its optimized conductance modulation characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the trade-off between symmetry and linearity of conductance modulation, enhances pattern recognition accuracy, and restricts sneak paths, enabling efficient operation in neuromorphic systems, particularly in crossbar array structures.
Implementation Method 1
the resistance change-based memristor has received great attention due to its simple two-terminal structure, low energy consumption per neuron activity, the possibility of implementing the analog synaptic weight modulation and the like
Implementation Method 2
a transistor and two-terminal variable resistance memory devices, where a separate memory voltage is applied to each device to control the gate voltage
Data Source
AI summary
The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.