Neuromorphic Synapse Weight Update via Delayed Pulse Sequences

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Solution Overview

Problem

Current methods for updating weights of synapses in neuromorphic devices, such as STDP using TDM or memristors, face challenges with slow update speed and low stability due to the need for synchronized timing cycles and normal operation of multiple memristors.

Innovation Solution

A method involving specific timing sequences of spikes and pulses inputted to transistors and memristors, with delayed inputs and gating pulses to update synapse weights efficiently, allowing for potentiation or depression of synapse weights in a short time and improving stability by using a single memristor per synapse.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TDM method is used to implement STDP, then synapse weight updating can be achieved, but update speed becomes very slow due to lengthy period requirements

Engineering Contradiction:
Improvesynapse weight updating capabilityVSAvoidupdate speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent uses periodic pulse signals with specific timing relationships to update synapse weights. By employing periodic row pulses and column pulses that overlap in time, the system achieves weight updating without requiring lengthy TDM cycles, thus improving update speed while maintaining reliability

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies preliminary action by pre-charging capacitors and preparing pulse sequences before the actual weight update operation. The row and column pulses are predetermined and timed to overlap appropriately, enabling fast weight updates without requiring lengthy real-time computation cycles

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple memristors are used for synapse weighting, then STDP method can be implemented, but update stability decreases because all memristors must operate normally

Engineering Contradiction:
ImproveSTDP implementation capabilityVSAvoidupdate stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent introduces transistors as intermediary elements between the pulse inputs and the single memristor. The transistors act as controlled switches that regulate the flow of row and column pulses to the memristor, providing stable and precise control over weight updates without requiring multiple memristors to operate simultaneously

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the synapse structure into distinct functional components: row selection transistors, column selection transistors, and a single memristor for weight storage. This segmentation allows independent control and optimization of each component, improving overall update stability while using fewer memristors

Inventive Principle:
Principle #1Segmentation

3Reliability

If synchronized timing cycles are used in TDM method, then global clock synchronization is achieved, but device complexity increases

Engineering Contradiction:
Improvetiming synchronizationVSAvoidtiming cycle complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the row pulse generation and column pulse generation into a unified timing scheme where both pulses are generated with predetermined time relationships. By combining these pulse sequences and allowing them to overlap, the system achieves synchronization without requiring complex separate TDM timing cycles for each direction

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10614355B2Method for updating weights of synapses of a neuromorphic device
Publication Date: 2020.04.07 SK HYNIX INC
  • US10614355B2 patent drawing
  • US10614355B2 patent drawing
  • US10614355B2 patent drawing

AI summary

A method for updating a weight of a synapse of a neuromorphic device is provided. The synapse may include a transistor and a memristor. The memristor may have a first electrode coupled to a source electrode of the transistor. The method may include inputting a row spike to a drain electrode of the transistor at a first time; inputting a column spike to a second electrode of the memristor at a second time; inputting a row pulse to the drain electrode of the transistor at a third time that is delayed by a first delay time from the second time; inputting a column pulse to the second electrode of the memristor at a fourth time that is delayed by a second delay time from the second time; and inputting a gating pulse to a gate electrode of the transistor at a fifth time that is delayed by a third delay time from the fourth time.