Neuromorphic Hardware Validation Using Temporal Queue Assertions
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Solution Overview
Problem
The verification of neuromorphic hardware, which includes neural network accelerators with parallel components and queue structures, is complex and error-prone due to the lack of a traditional sequential instruction model, making it difficult to validate the correct functioning of these systems.
Innovation Solution
A method is provided for simulating and validating neuromorphic hardware using horizontal and vertical assertions that define how the machine operates in both spatial and temporal dimensions, ensuring the correct delivery and ordering of packets in queue structures, and incorporating metadata to track data propagation across time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verification methods are used for neuromorphic hardware, then the verification process is simple and follows sequential instruction models, but the verification is incomplete and error-prone due to the lack of sequential instruction model in parallel queue structures
Solution Approach 1:
The patent introduces a temporal dimension to the verification process by tracking queue states across multiple time steps. Instead of verifying only the final state, the system constructs a directed graph that evolves over time, adding a time dimension to the state verification. This allows comprehensive validation of parallel queue structures without requiring sequential instruction models.
Solution Approach 2:
The patent introduces an intermediary verification layer that mediates between the complex parallel hardware operations and the validation process. The directed graph serves as an intermediary representation that captures the essence of queue operations without requiring direct inspection of complex hardware interactions. This intermediary model simplifies the verification task while maintaining accuracy.
2Productivity
If parallel queue structures are used in neuromorphic hardware, then processing capacity and speed are improved, but timing issues and packet mix-ups become more difficult to detect and validate
Solution Approach 1:
The patent implements feedback mechanisms where the verification system continuously monitors queue states and compares them against expected states derived from the neural network specification. The directed graph captures the feedback loop of data flow through queues, allowing the system to detect timing issues and packet mix-ups by comparing actual queue contents with expected contents at each time step.
Solution Approach 2:
The patent replaces traditional mechanical verification approaches (step-by-step instruction tracing) with a mathematical/graph-based verification system. Instead of mechanically following instruction sequences, the system uses directed graphs and state transitions to mathematically model and verify queue operations, making timing validation more systematic and less error-prone.
3Measurement precision
If comprehensive assertion testing is performed at each time step, then validation accuracy is improved, but computational overhead and verification time increase
Solution Approach 1:
The patent segments the verification process into discrete time steps, where assertions are tested at each individual time step rather than only at the end. This segmentation allows the verification to be broken down into manageable chunks, improving accuracy by catching errors early while allowing parallel execution of verification checks at each segment, thus mitigating the time overhead.
Data Source
AI summary
Simulation and validation of neural network systems is provided. In various embodiments, a description of an artificial neural network is read. A directed graph is constructed comprising a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computing function of the neural network system. A graph state is updated over a plurality of time steps according to the description of the neural network, the graph state being defined by the contents of each of the plurality of queues. Each of a plurality of assertions is tested at each of the plurality of time steps, each of the plurality of assertions being a function of a subset of the graph state. Invalidity of the neural network system is indicated for each violation of one of the plurality of assertions.