Neuromorphic Winner-Take-All Encoding for Low Power Computation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current neuromorphic systems face challenges in efficiently computing the largest value among multiple inputs with high dynamic range and high input rates, leading to increased power consumption and hardware complexity, particularly in Winner Takes All (WTA) operations.
Innovation Solution
The implementation of Thermometer-Coded Pairwise Binary (TCPB) coding scheme and winner-take-all (WTA) networks that convert population codes into TCPB codes, allowing for efficient comparison and reducing the number of required cores and power consumption, with a scalable and compact winner-take-all system that uses small numbers of cores even for large inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional Winner Takes All (WTA) operations are used to compute the largest value among multiple inputs, then the system can identify the maximum value, but the power consumption and hardware complexity increase significantly
Solution Approach 1:
The patent transforms the input representation from standard binary or population codes into a specialized encoding format that enables more efficient WTA computation. By changing the parameter representation of input values, the system achieves accurate maximum value detection while reducing the computational complexity and power consumption of the WTA operation.
Solution Approach 2:
The patent divides the WTA computation process into multiple stages or segments, processing inputs in a hierarchical manner. This segmentation allows the system to eliminate candidates progressively rather than comparing all inputs simultaneously, thereby reducing the overall hardware complexity and energy consumption while maintaining computation accuracy.
2Productivity
If conventional WTA operations are used with high input rates and high dynamic range, then the system can process diverse inputs quickly, but the hardware complexity increases
Solution Approach 1:
The patent segments the WTA operation into multiple processing stages that can operate in parallel. By dividing the comparison process into hierarchical levels where intermediate results are combined progressively, the system achieves high input processing rates without requiring proportionally complex hardware, as each stage processes a subset of inputs independently.
Solution Approach 2:
The patent introduces an additional dimensional aspect to the WTA computation by using a multi-stage hierarchical structure. Instead of a single-layer brute-force comparison, the system adds temporal or structural dimensions to the computation process, allowing high-rate processing through parallel staged operations rather than simultaneous full-comparison hardware.
3Measurement precision
If standard WTA operations are used, then the winner can be identified, but the computation delay is reduced only by half with the new approach
Solution Approach 1:
The patent performs preliminary encoding and preprocessing of input values before the actual WTA comparison. By preparing inputs in advance in a specialized format and organizing them into hierarchical groups, the system reduces the computation delay of the critical comparison path while maintaining accurate winner identification through pre-organized data structures.
Solution Approach 2:
The patent segments the winner identification process into multiple parallel comparison stages. By dividing the full set of inputs into subsets that are processed in hierarchical stages, the system achieves faster overall computation delay compared to sequential or simultaneous full-comparison methods, while maintaining precise winner identification through progressive elimination.
Data Source
AI summary
Neurosynaptic systems for computing characteristics of a set are provided. In various embodiments, a plurality of encoders is provided. Each encoder is adapted to receive a population coded input and generate an encoded output. The encoded output comprises a plurality of segments. Each segment corresponds to one or more binary bits. A winner selection component is adapted to receive the encoded outputs from the plurality of encoders and to perform a method comprising: proceeding from highest order to lowest order of the segments of the encoded outputs of the encoders, performing a bitwise OR operation across all segments of equivalent order; disqualifying each encoded output whose bits do not match the result of the bitwise OR operation across all segments of equivalent order; outputting remaining encoded outputs.