Artificial Neuron MAC Circuit for Bitmap-Based Non-Zero Multiplication
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Solution Overview
Problem
Current artificial neural networks require significant memory and computational resources due to the large number of multipliers needed for multiplication operations between weight and synapse values, which increases the complexity and cost of integrated circuits, especially as network size grows.
Innovation Solution
The implementation of a bitwise logical AND operation using an AND gate array and storage devices to identify and multiply only non-zero elements (NZPs) in weight and synapse matrices, reducing the number of multipliers and memory required through the use of a bitmap-based compression method that allows direct access to non-zero elements without decompression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional multiplication operations are performed for all weight and synapse values, then complete computational accuracy is achieved, but the number of multipliers and memory size increase significantly
Solution Approach 1:
The patent extracts and processes only the non-zero elements from weight and synapse values, separating them from zero elements. By identifying and processing only the meaningful non-zero components through bitmap tracking, the system eliminates the need for multipliers handling zero values, thus reducing the number of multipliers while maintaining computational accuracy for actual contributions.
Solution Approach 2:
Instead of performing multiplication operations on all N weight-synapse pairs, the patent applies partial action by only processing pairs where both weight and synapse values are non-zero. This selective processing reduces computational overhead and multiplier requirements while maintaining accuracy for the subset of operations that actually contribute to the result.
2Quantity of substance
If zero-skipping is applied to weight values only, then memory size for weight matrix is reduced, but synapse values still require full storage and processing
Solution Approach 1:
The patent merges the zero-skipping optimization for both weight and synapse values into a unified processing framework. By applying the same bitmap-based non-zero element identification to both matrices and coordinating their processing through AND gate operations on their respective bitmaps, the system achieves synergistic reduction in memory requirements and computational throughput improvement that exceeds applying zero-skipping to only one matrix.
3Quantity of substance
If bitmap-based compression is used to store only non-zero elements, then memory size is reduced, but access complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing bitmap representations of non-zero elements during data preparation. These bitmaps are generated in advance and stored alongside the compressed non-zero element data, enabling rapid identification of valid elements during processing without adding complexity to the access operation. The preliminary preparation of bitmaps transforms what would be a complex search problem into a simple bitwise AND operation.
4Device complexity
If the number of multipliers is reduced by skipping zero elements, then device area and power consumption decrease, but computational overhead for identifying non-zero elements increases
Solution Approach 1:
The patent replaces the mechanical/computational approach of checking each element individually with a bitwise logical AND operation on pre-computed bitmaps. This substitution transforms a potentially expensive element-by-element checking process into a highly efficient parallel bitwise operation that can be executed in a single clock cycle, eliminating the computational overhead concern while maintaining reduced multiplier counts.
Data Source
AI summary
An acceleration apparatus applied in an artificial neuron is disclosed. The acceleration apparatus comprises an AND gate array, a first storage device, a second storage device and a multiply-accumulate (MAC) circuit. The AND gate array with plural AND gates receives a first bitmap and a second bitmap to generate an output bitmap. The first storage device stores a first payload and outputs a corresponding non-zero first element according to a first access address associated with a result of comparing the first bitmap with the output bitmap. The second storage device stores a second payload and outputs a corresponding non-zero second element according to a second access address associated with a result of comparing the second bitmap with the output bitmap. The MAC circuit calculates a dot product of two element sequences from the first storage device and the second storage device.