Neuron Smearing in Deep Learning Accelerators
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Solution Overview
Problem
Current deep learning technologies face challenges in achieving improvements in accuracy, performance, and energy efficiency, particularly in the training and inference processes of neural networks, where existing methods lack efficiency and scalability.
Innovation Solution
The implementation of a deep learning accelerator system that utilizes a fabric of processing elements with compute engines and routers, enabling dataflow-based processing and instruction-based communication, allows for the allocation of processing elements to perform computations across multiple nodes of a dataflow graph, using wavelets for communication and virtual channels for data transfer, facilitating parallel computations and reduced wall-clock times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single neuron is implemented using resources of multiple processing elements, then computational performance and parallelism are improved, but implementation complexity and resource allocation difficulty increase
Solution Approach 1:
The patent divides a single neuron's computational workload into multiple segments that can be distributed across different processing elements. Each processing element handles a portion of the neuron's computations, allowing parallel execution while maintaining the logical integrity of the neuron. This segmentation enables high-performance computation without requiring a one-to-one mapping between neurons and processing elements.
Solution Approach 2:
The patent creates processing elements that can serve multiple functions - they can implement portions of different neurons, handle various computational operations (multiplication, accumulation, activation functions), and dynamically reconfigure based on workload requirements. This multi-functionality allows the same hardware resources to be flexibly allocated across multiple neurons and computational tasks.
2Use of energy by moving object
If computational load is balanced across processing elements, then energy efficiency and resource utilization are improved, but load balancing complexity and coordination overhead increase
Solution Approach 1:
The patent implements self-service mechanisms where processing elements autonomously monitor their own workload, detect imbalances, and dynamically adjust their task allocation. Each processing element can request additional work when underutilized or shed work when overloaded, without requiring centralized control. This self-regulating approach achieves load balancing while minimizing coordination overhead and energy consumption.
3Productivity
If neuron smearing is implemented to improve performance, then training and inference speed are improved, but maintaining accuracy and convergence properties becomes more difficult
Solution Approach 1:
The patent incorporates feedback mechanisms where the system continuously monitors computational accuracy, convergence metrics, and performance parameters during neuron smearing operations. Based on this feedback, the system dynamically adjusts the degree of smearing, the distribution of computational tasks, and the precision of arithmetic operations to maintain accuracy while maximizing performance benefits.
Solution Approach 2:
The patent dynamically changes key parameters such as numerical precision (floating-point vs. integer arithmetic), activation function approximation levels, and task distribution patterns based on the specific computational context, layer position in the network, and convergence stage. These parameter adjustments allow the system to optimize for speed when appropriate while maintaining accuracy when needed.
Data Source
AI summary
Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has memory. At least a first single neuron is implemented using resources of a plurality of the array of processing elements. At least a portion of a second neuron is implemented using resources of one or more of the plurality of processing elements. In some usage scenarios, the foregoing neuron implementation enables greater performance by enabling a single neuron to use the computational resources of multiple processing elements and/or computational load balancing across the processing elements while maintaining locality of incoming activations for the processing elements.