Neurosynaptic Core Placement for Power-Driven Synthesis
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Solution Overview
Problem
Power consumption and heat dissipation pose significant barriers to exascale computing in neurosynaptic networks, as existing arrangements do not effectively minimize power costs of communication while maintaining program semantics.
Innovation Solution
A power-driven synaptic network synthesis method that models power consumption as wire length, using a placement graph with edge weights based on spike frequency to optimize the arrangement of neurosynaptic cores and minimize edge lengths, thereby reducing power consumption and energy usage through a multilevel partitioning algorithm and fault-tolerant placement strategies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If neurosynaptic cores are arranged using default sequential placement, then device complexity is reduced and ease of manufacture is improved, but power consumption increases due to longer wire lengths and higher communication costs
Solution Approach 1:
The patent changes the optimization parameter from simple sequential placement to power-aware placement that minimizes wire length. By modeling power consumption as proportional to wire length and using this as the optimization criterion, the system achieves 30-83% power savings while maintaining manageable placement complexity through automated algorithms.
Solution Approach 2:
The patent performs preliminary placement optimization during the design phase using multilevel partitioning algorithms. By pre-calculating optimal core arrangements that minimize communication wire lengths before deployment, the system reduces runtime power consumption without adding operational complexity.
2Use of energy by moving object
If neurosynaptic cores are placed closer together to minimize wire length, then power consumption is reduced, but latency constraints may be violated due to increased congestion and longer critical paths
Solution Approach 1:
The patent applies multilevel partitioning that divides the neurosynaptic network into hierarchical clusters. This segmentation allows cores within clusters to be placed close together for low power, while maintaining larger spacing between clusters to satisfy latency constraints and reduce congestion on inter-cluster communication paths.
Solution Approach 2:
The patent implements local optimization where placement density and wire length minimization are applied locally within clusters, while global latency constraints are enforced at the system level. This allows aggressive power optimization in local regions without compromising overall timing requirements.
3Use of energy by moving object
If the network topology is optimized for minimum wire length, then power consumption decreases, but fault tolerance may be reduced due to less redundant communication paths
Solution Approach 1:
The patent implements dynamic fault tolerance by monitoring communication paths and dynamically rerouting spikes around faulty cores or routers. This allows the system to maintain low power consumption through optimized placement while preserving fault tolerance through adaptive runtime reconfiguration rather than static redundant paths.
4Use of energy by moving object
If multilevel partitioning is used to optimize placement, then power consumption is significantly reduced, but computational complexity and placement time increase
Solution Approach 1:
The patent uses multilevel partitioning that recursively divides the large-scale neurosynaptic network into smaller sub-problems. This segmentation transforms an intractable global optimization problem into a series of manageable local optimizations, achieving 30-83% power savings while keeping computational complexity tractable through divide-and-conquer.
Data Source
AI summary
Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.