Fault-Tolerant Neurosynaptic Core Placement via Wire Length Minimization
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Solution Overview
Problem
Power consumption and heat dissipation are significant barriers in exascale computing, and existing neurosynaptic networks face challenges in minimizing power costs while maintaining efficient communication and fault tolerance.
Innovation Solution
The method involves modeling power consumption as wire length in neurosynaptic networks, using a multi-level partitioning algorithm to minimize wire length and optimize core placement, and employing fault-tolerant techniques to avoid faulty locations and routers, thereby reducing overall power and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If default sequential placement is used, then placement simplicity is maintained, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-identifying faulty cores and routers before placement, then using this information to guide the placement algorithm. The multi-level partitioning algorithm performs preliminary partitioning of the network topology to create placement regions that avoid faulty areas, thereby minimizing wire length and power consumption before actual core placement occurs.
2Reliability
If faulty locations are avoided through placement blockage, then fault tolerance is improved, but available placement area decreases
Solution Approach 1:
The patent applies segmentation by dividing the network topology into multiple placement regions through multi-level partitioning. Each region is independently optimized to accommodate cores while avoiding faulty areas. This segmentation allows the system to distribute cores across multiple viable regions rather than losing all placement options when faulty areas are excluded.
3Use of energy by moving object
If wire length is minimized through optimization, then power consumption decreases, but placement computation time increases
Solution Approach 1:
The patent uses multi-level partitioning to segment the global placement problem into hierarchical sub-problems. The topology is partitioned at multiple levels, with each level optimizing placement within its scope. This segmentation reduces the computational complexity of finding the global optimum by breaking it into manageable local optimizations, thereby reducing computation time while still achieving significant wire length reduction.
Data Source
AI summary
Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.