Neurosynaptic Core with Error-Modulated STDP Learning
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Solution Overview
Problem
Conventional Spiking Neural Networks (SNNs) with Spike Time Dependent Plasticity (STDP) learning are inefficient and unsupervised, lacking adaptability and performance relevance to specific tasks.
Innovation Solution
A neurosynaptic processing core with STDP learning, comprising spiking neuron blocks, synapse blocks, and an STDP learning block that includes event accumulators, modifiers, and a learning error modulator to adjust synaptic weights based on spike events and errors, enabling on-chip learning with error modulated STDP rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional STDP learning is implemented in SNNs, then on-chip learning capability is achieved, but the learning process is unsupervised and indifferent to task performance
Solution Approach 1:
The patent introduces a feedback mechanism where the supervised error signal from the SNN task performance is fed back to modulate the STDP learning process. The learning error modulator receives the error signal and uses it to adjust the synaptic weight changes computed by the STDP mechanism, thereby making the unsupervised STDP process responsive to supervised task performance requirements.
2Extent of automation
If STDP learning rule is used to adjust synaptic weights, then learning occurs based on spike timing, but the process lacks supervision and task awareness
Solution Approach 1:
The patent merges the automatic synaptic weight adjustment capability of STDP with the task-specific guidance of supervised learning. The STDP learning block automatically computes weight changes based on spike timing, while the learning error modulator combines this with the supervised error signal, creating a hybrid mechanism that retains automation while gaining task-specific adaptability.
3Ease of manufacture
If conventional SNN systems implement STDP learning, then on-chip learning is enabled, but efficiency and effectiveness are insufficient
Solution Approach 1:
The patent segments the learning process into distinct functional blocks: the STDP learning block that handles automatic spike-time-based weight computation, the learning error modulator that processes supervised error signals, and the synaptic weight modifier that integrates both signals. This segmentation allows each component to be optimized independently while working together to achieve efficient and effective on-chip learning.
Data Source
AI summary
There is provided a neurosynaptic processing core with spike time dependent plasticity (STDP) learning for a spiking neural network, including: a spiking neuron block including a pre-synaptic block and a post-synaptic block; a synapse block communicatively coupled to the spiking neuron block; a STDP learning block communicatively coupled to the spiking neuron block and the synapse block, the STDP learning block including a pre-synaptic event accumulator including a pre-synaptic spike event memory block and a pre-synaptic spike parameter modifier; a post-synaptic event accumulator including a post-synaptic spike event memory block and a post-synaptic spike parameter modifier, a weight change accumulator, and a weight change parameter modifier; a learning error modulator; and a synaptic weight modifier configured to modify a synaptic weight parameter based on a weight change parameter and a learning error corresponding to the synaptic weight parameter. There is also provided a corresponding method of operating and a corresponding method of forming the neurosynaptic processing core.