Neurosynaptic Interconnect Circuit for Hybrid Processing
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Solution Overview
Problem
Traditional computing architectures separate memory and computation, limiting the integration of parallel and serial processing methods, which hampers efficient symbolic and sub-symbolic computing tasks such as pattern recognition and algorithmic operations.
Innovation Solution
A neuromorphic and synaptronic processing system that integrates multiple neurosynaptic core circuits for parallel processing with a serial processing device, coupled via an interconnect circuit for data exchange, allowing for the routing of serialized and de-serialized data packets between the two for efficient symbolic and sub-symbolic computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional von Neumann architecture separates memory and computation, then device complexity is reduced and ease of manufacture is improved, but processing efficiency for both symbolic and sub-symbolic tasks deteriorates
Solution Approach 1:
The system is segmented into distinct serial processing units and parallel neurosynaptic processing units, each optimized for specific task types. This allows the system to maintain manufacturing simplicity while achieving high processing efficiency through specialized architecture for different computational modes.
Solution Approach 2:
The patent merges traditional serial von Neumann architecture with parallel neurosynaptic architecture into a hybrid system. This combination enables the system to leverage both the programmability of serial processing and the parallel pattern recognition capabilities of neurosynaptic processing, resolving the contradiction between manufacturing simplicity and processing efficiency.
2Productivity
If memory and computation are integrated in neuromorphic architecture, then processing efficiency for pattern recognition is improved, but device complexity increases
Solution Approach 1:
The neurosynaptic processing is segmented into discrete core circuits with standardized structures. Each core circuit contains integrated memory and computation elements organized in a regular pattern, which simplifies manufacturing while maintaining the parallel processing efficiency needed for pattern recognition tasks.
3Adaptability or versatility
If parallel neurosynaptic processing is used for sub-symbolic computation, then pattern recognition capability is improved, but integration with serial symbolic computation deteriorates
Solution Approach 1:
An interconnect circuit acts as an intermediary between the serial processing units and parallel neurosynaptic processing units. This mediator handles data routing, synchronization, and protocol conversion, enabling seamless integration of symbolic and sub-symbolic computation without requiring complex direct integration between the diverse processing architectures.
Data Source
AI summary
The present invention provides a system comprising a neurosynaptic processing device including multiple neurosynaptic core circuits for parallel processing, and a serial processing device including at least one processor core for serial processing. Each neurosynaptic core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of synapse devices. The system further comprises an interconnect circuit for coupling the neurosynaptic processing device with the serial processing device. The interconnect circuit enables the exchange of data packets between the neurosynaptic processing device and the serial processing device.