New BSDL Algorithmic Scan Path Modification for SoC JTAG Testing
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Solution Overview
Problem
Current boundary scan description languages, such as BSDL/HSDL, are inadequate for describing complex dynamic scan chains and test procedures at the chip-level JTAG testing, particularly when transitioning from board-level to chip-level testing, as they rely on static descriptions and lack the necessary flexibility to accommodate dynamic scan path modifications.
Innovation Solution
The introduction of a new hardware description language, New BSDL (NSDL), which enables algorithmic descriptions of system-on-chip components and their interconnections, supports dynamic modification of the scan path through crossroad devices, and facilitates parallel access for testing, addressing the limitations of existing languages by providing a bottom-up approach and enhanced description capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If BSDL/HSDL is used to describe boundary scan registers, then board-level JTAG testing is efficient, but chip-level JTAG testing cannot accommodate dynamic scan path modifications
Solution Approach 1:
The patent introduces a dynamic scan chain description mechanism that allows the scan path configuration to be modified at runtime through control signals. The scan chain description language includes dynamic elements that can change the scan path configuration during testing, enabling adaptability for chip-level JTAG testing while maintaining a structured description format.
Solution Approach 2:
The patent modifies the scan chain description parameters to include dynamic control fields that enable runtime reconfiguration. By changing the parameter structure from static to dynamic, the description language can accommodate varying scan path requirements for different testing scenarios without increasing overall complexity significantly.
2Adaptability or versatility
If a static ordered list of cells is used to compose the boundary scan register, then the description is simple, but complex dynamic scan chains required in IJTAG cannot be described
Solution Approach 1:
The patent segments the scan chain description into multiple components: a static base structure and dynamic configuration elements. This segmentation allows the simple ordered list to be extended with dynamic control information, enabling complex scan chain descriptions while preserving the clarity of the basic structure.
Solution Approach 2:
The patent implements a nested description structure where the dynamic control information is embedded within the static cell list framework. This nesting allows test procedure information to be included within the scan chain description without losing the hierarchical organization, preserving information while enabling dynamic behavior.
3Productivity
If BSDL/HSDL is used for board-level JTAG, then testing is efficient, but no space is provided for describing test procedures needed for each component
Solution Approach 1:
The patent creates a universal description language structure that can handle both board-level and chip-level JTAG testing requirements. The enhanced language includes optional fields for test procedure descriptions that can be activated when needed, maintaining compatibility with existing BSDL/HSDL while adding capability for component-specific test procedures.
Data Source
AI summary
The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.