Next Fetch Predictor Circuit for Short Branches and Return Fetch Groups
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Solution Overview
Problem
Existing processor circuits face inefficiencies in handling multiple control transfer instructions within a fetch group, leading to wasted processing time and power due to repeated fetching and discarding of instructions, especially in cases of short backward, forward, and return fetch groups.
Innovation Solution
An instruction fetch circuit is configured to identify and alter the order of instructions within a fetch group based on the type of control transfer instruction, such as replicating loops, omitting unnecessary instructions, and using return and branch prediction circuits more efficiently to reduce redundant fetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential fetching is used, then power consumption is reduced, but processor bandwidth and execution efficiency deteriorate due to repeated fetching and discarding of instructions in control transfer scenarios
Solution Approach 1:
The patent applies preliminary action by predicting control transfer instructions before they are executed. The branch prediction circuit anticipates branch outcomes and pre-fetches instructions from predicted target addresses, while the return fetch stack pre-loads return addresses for function calls. This allows the processor to continue fetching instructions proactively rather than stalling等待 control transfer completion, thereby improving processor bandwidth without proportionally increasing power consumption.
Solution Approach 2:
The patent implements dynamics by making the instruction fetch process adaptive rather than static. The system dynamically adjusts fetch behavior based on detected control transfer patterns: when a branch is predicted taken, fetching switches to the target address; when not taken, sequential fetching continues. The return fetch stack dynamically manages return addresses based on call/return instruction detection, allowing the fetch mechanism to flexibly respond to different control flow scenarios, improving efficiency while managing power usage.
2Productivity
If branch prediction circuits are used to predict control transfer instructions, then processor bandwidth is improved, but device complexity increases due to additional prediction logic and fetch management structures
Solution Approach 1:
The patent applies segmentation by dividing the control transfer handling into distinct functional components: the branch prediction circuit handles forward and backward branches, while the return fetch stack specifically manages function call/return sequences. This segmentation allows each component to be optimized for its specific purpose, managing complexity through modular design rather than a monolithic control structure.
Solution Approach 2:
The return fetch stack acts as an intermediary structure between the instruction fetch circuit and the execution units. It stores return addresses and enables the fetch circuit to proactively retrieve instructions that will be needed after function returns, without requiring complex real-time analysis of control flow. This intermediary simplifies the overall system by providing a buffer that manages the complexity of nested function calls.
3Productivity
If instructions are fetched in groups assuming sequential execution, then fetch efficiency is improved, but accuracy deteriorates when control transfer instructions are present in the fetch group
Solution Approach 1:
The system performs preliminary detection of control transfer instructions within fetch groups. Before fully committing to sequential execution of a fetched group, the branch prediction circuit analyzes the instructions to identify potential branches. This preliminary action allows the system to adjust the fetch address proactively, preventing the fetching of unnecessary instructions and improving both efficiency and accuracy.
Solution Approach 2:
The patent implements feedback mechanisms where the branch prediction circuit continuously monitors executed instructions and updates its predictions. When control transfer instructions are detected in fetched groups, the system uses feedback from actual branch outcomes to refine future predictions. The return fetch stack similarly uses feedback from call/return instruction detection to manage the stack contents, improving the accuracy of return address prediction while maintaining fetch efficiency.
Data Source
AI summary
An apparatus includes an instruction cache circuit and an instruction fetch circuit. The instruction fetch circuit is configured to retrieve, from the instruction cache circuit, a fetch group that includes a plurality of instructions for execution by a processing circuit, and to make a determination that the fetch group includes a control transfer instruction that is predicted to be taken. A target address associated with the control transfer instruction is directed to an instruction within the fetch group. The instruction fetch circuit is further configured to, based on the determination, alter instructions within the fetch group in a manner that is based on a type of the control transfer instruction.