NFC Reader Receiver Clock Phase Alignment Circuit
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Solution Overview
Problem
Near field communication (NFC) technologies face challenges in minimizing phase differences between sampling clock signals and received signals, leading to increased design complexity and device size due to the use of delay locked loops (DLLs).
Innovation Solution
A reader receiver system that generates multiple delayed clock signals by controlling the phase of an initial clock signal, selects the most closely aligned signal as the sample clock, and converts input signals into base band signals using I and Q phase sample clock signals, thereby minimizing phase noise and optimizing reception performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay locked loop (DLL) is used to minimize phase difference between sampling clock signal and received signal, then phase alignment is improved, but design complexity and device size increase
Solution Approach 1:
The DLL is segmented into functional blocks: initial clock generator, clock delay circuit with multiple delay cells, phase comparator, and selector. This modular segmentation allows each component to be optimized independently while reducing overall design complexity.
Solution Approach 2:
Instead of using a full DLL with continuous phase adjustment, the patent uses a simplified approach with a finite number of discrete delay stages (e.g., 4-8 delay cells). This partial action provides sufficient phase alignment for NFC applications without the complexity of continuous adjustment mechanisms.
2Measurement precision
If a delay locked loop (DLL) is used to minimize phase difference between sampling clock signal and received signal, then phase alignment is improved, but device size increases
Solution Approach 1:
The clock delay circuit uses nested delay cells where each cell is contained within the previous stage. This nesting approach minimizes the overall area by efficiently packing the delay elements, reducing the device size compared to traditional DLL implementations.
Solution Approach 2:
By segmenting the delay function into discrete, compact delay cells arranged in series, the patent reduces the total area required for phase alignment circuitry while maintaining sufficient phase adjustment capability for NFC reception.
3Measurement precision
If multiple delayed clock signals are generated with fine phase intervals, then phase alignment precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a moderate number of delay stages (e.g., 4-8 cells) that provide sufficient phase control precision for NFC applications without implementing an excessive number of stages that would increase complexity. This partial action achieves the required phase alignment accuracy with manageable circuit complexity.
Solution Approach 2:
The system dynamically selects the optimal delay stage based on phase detection feedback, allowing fine phase control without requiring all possible delay stages to be simultaneously present. This dynamic selection reduces the number of required circuit elements while maintaining precision.
Data Source
AI summary
Reader receivers including a sample clock providing unit are provided. The sample clock providing unit may be configured to generate a plurality of first clock signals of equivalent frequency that are out-of-phase relative to each other and further configured to generate first and second sample clock signals of unequal phase from selected ones of the plurality of first clock signals by comparing a respective phase of each of the plurality of first clock signals against a phase of a reference clock signal.