NFC Card Clock Recovery with Phase Offset Correction
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Solution Overview
Problem
Existing NFC card transceivers face challenges in maintaining accurate phase locking to the reader signal during both receiving and transmission modes, especially in clock-less designs, which is crucial for interoperability with legacy readers and enabling cost-effective, battery-efficient NFC applications.
Innovation Solution
A card clock recovery system with a phase lock loop (PLL) and a phase offset correction unit that compensates for the matching network memory effect by averaging phase error signals and adjusting the phase offset, ensuring accurate phase synchronization during both receiving and transmission modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a clock-less Card Emulation ALM transceiver is used to reduce cost and improve battery efficiency, then manufacturing cost and energy consumption are reduced, but phase accuracy deteriorates making it impossible to achieve the required +/- 10° phase error without reference clocks
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing phase offset values in a lookup table before actual transmission occurs. The phase offset compensation unit retrieves pre-computed compensation values based on measured phase errors, allowing the system to achieve accurate phase alignment without requiring expensive reference clocks or crystals during operation.
2Reliability
If phase locking is maintained during transmission mode to ensure continuous synchronization, then phase accuracy is improved, but the ability to accurately track reader phase information deteriorates because the card transmitter corrupts the reader phase signal
Solution Approach 1:
The patent segments the phase detection process into two distinct operational modes: during reception, the system detects reader phase information through the matching network; during transmission, it uses pre-computed phase offset values from a lookup table. This segmentation allows the system to maintain continuous phase locking while avoiding the corruption problem that occurs when attempting to detect reader phase during active transmission.
Solution Approach 2:
The patent introduces a phase offset compensation unit as an intermediary between the phase error detection and the PLL control. This intermediary retrieves compensation values from a pre-computed lookup table and applies them to correct the phase error signal, effectively mediating between the corrupted transmission-phase measurements and the required accurate phase locking.
3Speed
If Active Load Modulation is used to increase communication distance and reduce antenna size, then communication range is improved and antenna size is reduced, but phase accuracy deteriorates requiring extremely precise phase locking that is difficult to achieve
Solution Approach 1:
The patent applies preliminary action by pre-calculating phase offset compensation values for various transmission conditions and storing them in a lookup table. This allows the ALM transmitter to achieve the required +/- 10° phase accuracy by retrieving pre-computed values rather than relying on expensive reference clocks or complex real-time phase measurement during transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system enables stable and accurate phase locking to the reader signal, even during transmission, improving interoperability and reducing phase errors, thus supporting cost-effective NFC applications without reference clocks or crystals.
Implementation Method 1
a phase lock loop (PLL) having: a phase detector (PFD) configured to receive a reference input signal (512) and a loop feedback input signal (514), and to provide a phase error signal (518) representing a phase difference between the reference input signal (512) and the loop feedback input signal (514)
Implementation Method 2
a loop filter (520) configured to receive a corrected phase error signal (756), and to provide a filtered corrected phase error signal (526)
Implementation Method 3
a controllable oscillator (530) configured to receive the filtered corrected phase error signal (526), and to provide a controlled frequency output signal (534)
Implementation Method 4
The phase offset computation unit is configured (i) to store a plurality of first phase error signals sampled at plural first discrete points in time, to compute a first average out of these stored first phase error signals
Implementation Method 5
a card matching network (475) coupled to a card antenna (490), to output a receiver, RX, input signal (476) generated during a receiving mode of the NFC card transceiver (450)
Data Source
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AI summary
Disclosed is a card clock recovery system (480; 500) for use in an NFC card transceiver (150; 450), wherein the NFC card transceiver (150; 450) is couplable to an NFC reader (110; 410). The card clock recovery system (480; 500) has: a phase lock loop (505) having: a phase/frequency detector (510), which is configured to receive a reference signal (512) provided at an RX port (476) of a matching network (475) during a receiving mode of the NFC transceiver (150; 450) or to receive a reference signal provided at the RX port (476) of the matching network (475) during a transmission mode of the NFC transceiver (150; 450), to receive a loop feedback signal (538), and to provide a phase error signal (518) that represents a phase difference between the reference signal (512) and the loop feedback signal (538); a loop filter (520) configured to receive a corrected phase error signal (756) that is derived from the phase error signal (518), and to provide a filtered corrected phase error signal (526); a controllable oscillator (530), which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal (534), which is provided as the card clock generation control signal (539) to a card clock generation unit (485) of an NFC card transceiver (150; 450), and as the loop feedback signal (538), via the loop feedback line (536), to the phase/frequency detector (510). The card clock recovery system (480; 500) further has a phase offset correction unit (700), which is configured to receive the phase error signal (518) provided by the phase/frequency detector and to provide the corrected phase error signal (756) to the loop filter (520), and which has a phase error sampling unit (720), a phase offset computation unit (730), and a phase subtractor unit (740).