NFC Card Clock Recovery with Phase Offset Correction for ALM

Solution Overview

Problem

Near Field Communication (NFC) card transceivers face challenges in maintaining phase lock with the reader signal during both receiving and transmission modes, especially when using Active Load Modulation (ALM) systems with small antennas, which require accurate phase alignment to interoperate with legacy readers and conserve battery life without external clocks or crystals.

Innovation Solution

A card clock recovery system incorporating a phase lock loop with a phase/frequency detector, loop filter, controllable oscillator, and phase offset correction unit, which samples phase errors at discrete points, computes and subtracts offsets to provide a corrected phase error signal, ensuring accurate phase locking during both receiving and transmission modes without external reference clocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a phase lock loop is used for clock recovery without external reference clocks, then cost and power consumption are reduced, but phase accuracy deteriorates during transmission mode

Engineering Contradiction:

Improvepower consumptionVSAvoidphase accuracy

Core Design Contradiction:

Loss of energyVSMeasurement precision

Solution Approach 1:

The system performs preliminary phase calibration during receiving mode before transmission begins. The phase offset correction unit stores calibration values obtained when the matching network is in its initial state, which are then applied during transmission mode to compensate for phase shifts caused by transmitter activation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The phase lock loop continuously monitors phase errors and feeds this information back to the controllable oscillator to maintain phase lock. Additionally, the system measures phase shifts during transmission and uses this feedback to update correction values for subsequent operations.

Inventive Principle:

Principle #23Feedback

2Measurement precision

If phase calibration is performed continuously, then phase accuracy is improved, but system complexity and processing time increase

Engineering Contradiction:

Improvephase alignment accuracyVSAvoidsystem complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Instead of continuous calibration, the system performs phase calibration periodically at discrete points in time - specifically during receiving mode before transmission and at controlled intervals during transmission mode. This periodic approach maintains accuracy while reducing computational burden.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The system performs preliminary phase calibration during receiving mode before transmission begins. The phase offset correction unit stores calibration values obtained when the matching network is in its initial state, which are then applied during transmission mode to compensate for phase shifts caused by transmitter activation.

Inventive Principle:

Principle #10Preliminary action

3Stability of the object's composition

If the matching network memory effect is compensated in real-time, then phase lock stability is improved, but processing time and computational load increase

Engineering Contradiction:

Improvephase lock stabilityVSAvoidprocessing time

Core Design Contradiction:

Stability of the object's compositionVSLoss of time

Solution Approach 1:

The system performs preliminary phase calibration during receiving mode before transmission begins. The phase offset correction unit stores calibration values obtained when the matching network is in its initial state, which are then applied during transmission mode to compensate for phase shifts caused by transmitter activation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of continuous calibration, the system performs phase calibration periodically at discrete points in time - specifically during receiving mode before transmission and at controlled intervals during transmission mode. This periodic approach maintains accuracy while reducing computational burden.

Inventive Principle:

Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables NFC card transceivers to maintain accurate phase alignment with the reader signal during transmission, improving interoperability with legacy readers and extending battery life by eliminating the need for external clocks or crystals, thus enhancing the performance and cost-effectiveness of NFC systems.

Implementation Method 1

a phase/frequency detector (PFD), which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive, via a loop feedback line, a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal

Methodology Applied

Scientific EffectPhase detection:

Implementation Method 2

a controllable oscillator, CO, which is configured to receive the filtered corrected phase error signal (for example as a commanding control input signal) and to provide a controlled frequency output signal

Methodology Applied

Scientific EffectOscillation:

Implementation Method 3

a phase offset correction unit, which is configured to receive the phase error signal provided by the PFD and to provide the corrected phase error signal to the loop filter

Methodology Applied

Scientific EffectPhase offset correction:

Data Source

PatentUS11849018B2System and method of clock recovery with low phase-error for card emulation clock-less NFC transceivers

Publication Date: 2023.12.19 NXP BV

AI summary

Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.