Reconfigurable NFC PLL Clock Switching for P2P Synchronization
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Solution Overview
Problem
Conventional Near Field Communication (NFC) systems require large silicon area and high current consumption due to separate clock generation for the NFC reader and card, and complex clock synchronization in P2P active mode, which is inefficient and costly.
Innovation Solution
A reconfigurable Phase Locked Loop (PLL) circuit with a multiplexer and clock extractor that dynamically switches between a reference clock and an NFC H-Field extracted clock, allowing for synchronous switching in P2P active mode without the need for complex clock swapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock generation schemes are used for NFC reader and card, then clock synchronization is achieved, but silicon area and current consumption increase
Solution Approach 1:
The patent merges the reader clock and card clock generation into a single reconfigurable PLL circuit. The PLL can be configured to lock to either a reference clock (for reader mode) or an extracted NFC H-Field clock (for card mode), eliminating the need for separate clock generation circuits and reducing silicon area while maintaining synchronization reliability.
Solution Approach 2:
The reconfigurable PLL serves multiple functions by being able to operate in different modes: locked to reference clock for reader operations, locked to extracted clock for card operations, and dynamically switched for P2P active mode. This multi-functionality replaces what would traditionally require separate dedicated circuits.
2Reliability
If both reader clock and card clock are enabled concurrently in P2P Active mode, then TX and RX Frame Delay Timing is met, but current consumption increases
Solution Approach 1:
The patent implements dynamic switching capability where the PLL can rapidly reconfigure between locking to the reference clock and locking to the extracted clock based on whether TX or RX operations are active. This dynamic operation allows meeting stringent Frame Delay Timing requirements while consuming less current by activating only the necessary clock path at any given moment.
3Reliability
If digital baseband circuit performs synchronized clock switching, then continuous clocks are ensured to digital circuit, but device complexity and current consumption increase
Solution Approach 1:
The patent introduces a multiplexer as an intermediary component that selectively routes either the reference clock or the extracted NFC H-Field clock to the PLL input based on the operational mode. This simple intermediary mechanism enables seamless clock switching without requiring complex digital baseband intervention, reducing both device complexity and current consumption while ensuring continuous clock supply.
Data Source
AI summary
A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock.