NFC PLL Control for Stable Phase Tracking Under Load Modulation
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Solution Overview
Problem
Current NFC technologies face challenges in power consumption and communication efficiency, particularly when using local clock generators and recovered clock signals for phase-locked loops, which can result in discontinuous carrier signals and poor modulation depth, affecting communication between NFC devices.
Innovation Solution
An NFC apparatus and method that includes a clock extractor for field clock recovery, a digital phase-locked loop for frequency tracking, and a controller for selective open-loop or closed-loop control based on frequency or phase detection, generating open-loop control signals to maintain stable phase tracking during discontinuous carrier signals and normal modulation depths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a local clock generator is used to provide the carrier signal for the mobile phone, then the phase-locked loop can operate continuously, but extra power consumption is caused
Solution Approach 1:
The patent implements dynamic switching between open-loop and closed-loop control modes of the phase-locked loop based on real-time detection of carrier signal continuity. When the carrier signal is continuous, the system operates in closed-loop mode for power saving; when the signal becomes discontinuous, it switches to open-loop mode to maintain phase tracking stability, thus adapting the system behavior to varying operational conditions
Solution Approach 2:
The patent changes the control mode parameter of the phase-locked loop dynamically. By detecting carrier signal characteristics and adjusting the PLL control mode between open-loop and closed-loop states, the system optimizes the balance between power consumption and phase tracking reliability based on actual signal conditions
2Use of energy by moving object
If the phase-locked loop uses a recovered clock signal from the carrier signal, then power consumption is reduced, but the output may be unideal when modulation depth is large or during active load modulation
Solution Approach 1:
The patent employs feedback mechanisms by continuously detecting the frequency and phase of the recovered clock signal, and based on this feedback, dynamically adjusting the PLL control mode. When detection indicates ideal conditions, closed-loop operation maintains power efficiency; when deviations are detected, the system switches to open-loop mode to ensure reliable phase tracking
Solution Approach 2:
The system dynamically adapts its operation by switching between closed-loop and open-loop control modes based on real-time signal quality assessment. This dynamic adjustment allows the system to maintain power efficiency under normal conditions while ensuring reliability when signal conditions deteriorate due to large modulation depths or active load modulation
3Use of energy by moving object
If closed-loop control is always used on the digital phase-locked loop, then power consumption is reduced, but communication is affected when the carrier signal is discontinuous
Solution Approach 1:
The patent implements dynamic control mode switching where the PLL operates in closed-loop mode during normal continuous signal conditions to save power, and automatically transitions to open-loop mode when discontinuities are detected in the carrier signal, thus balancing power consumption and communication reliability based on real-time signal characteristics
Solution Approach 2:
The system uses feedback from carrier signal detection to control the PLL operation mode. The detection unit continuously monitors signal continuity and provides feedback to the control unit, which adjusts the PLL mode accordingly - maintaining closed-loop operation for power efficiency when signals are continuous, and switching to open-loop when discontinuities threaten communication quality
Data Source
AI summary
A near-field communication (NFC) apparatus includes a clock extractor configured to perform clock recovery based on a first carrier signal sent by an NFC card reader to obtain a field clock signal; a digital phase-locked loop configured to perform frequency tracking on the field clock signal to output a first clock signal; a digital baseband chip configured to perform load modulation based on the first clock signal to generate a second carrier signal; and a controller configured to detect a frequency or a phase of the field clock signal, and selectively perform open-loop control on the digital phase-locked loop based on a detection result.