NFC Synchronization Circuit for Spurious-Tone-Free Carrier Lock

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Solution Overview

Problem

Existing near-field communication devices suffer from spurious tones in the output signal due to analog or digital control of oscillators, which degrade communication quality.

Innovation Solution

A synchronization circuit with a phase-locked loop that includes a digitally controlled oscillator and a frequency matching circuit, clocked by a higher frequency clock signal, to synchronize and control the oscillator, reducing spurious tones and improving signal quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If an analog or digital controlled oscillator is used to generate the carrier signal, then the oscillator can be servo-controlled to match the reference frequency, but spurious tones appear in the output signal degrading communication quality

Engineering Contradiction:
Improvefrequency matching precisionVSAvoidspurious tones
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent divides the phase-locked loop into two separate domains: a first domain clocked by the reference frequency signal that generates the carrier signal and frequency information, and a second domain clocked by a higher frequency clock signal that performs the frequency comparison and control. This segmentation prevents spurious tones from appearing at the carrier frequency while maintaining precise frequency matching capability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the phase-locked loop is clocked by the reference frequency signal, then the system operates at the carrier frequency, but the loop speed and responsiveness are limited

Engineering Contradiction:
Improvephase-locked loop speedVSAvoidsynchronization time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a second domain that operates at a higher frequency dimension (clocked by a clock signal with frequency higher than the reference frequency) to perform the frequency comparison and control operations. This allows the phase-locked loop to respond faster and achieve synchronization more quickly, while the first domain continues to generate the carrier signal at the reference frequency without spurious tones.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively removes spurious tones from the carrier signal, enhancing communication readability and responsiveness by using a higher frequency clock to improve the phase-locked loop's speed and efficiency.

Implementation Method 1

A synchronization circuit with a phase-locked loop that includes a digitally controlled oscillator and a frequency matching circuit, clocked by a higher frequency clock signal, to synchronize and control the oscillator

Methodology Applied
Scientific EffectPhase-locked loop: Feedback

Implementation Method 2

a first domain including a digitally controlled oscillator configured to generate a signal at a given frequency

Methodology Applied
Scientific EffectElectromagnetic oscillation: Electromagnetic Induction

Data Source

PatentUS20260045953A1Device comprising a synchronization circuit for performing near field communication
Publication Date: 2026.02.12 STMICROELECTRONICS (GRENOBLE 2) SAS
  • US20260045953A1 patent drawing
  • US20260045953A1 patent drawing
  • US20260045953A1 patent drawing

AI summary

A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.