Dual-Gate NFET Power Amplifier Biasing for High Psat Reliability
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Solution Overview
Problem
Current power amplifiers struggle to reliably achieve high saturation power (Psat) required for RFICs operating in new frequency bands, such as the 13 GHz band, where Psat demands are approximately 28 dBm.
Innovation Solution
A circuit structure incorporating a power amplifier with a biasing scheme that includes multiple voltage generators and parallel transistor chains with N-type field effect transistors (NFETs) connected in series, utilizing both front and back gates for biasing to achieve high power output without violating reliability specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional power amplifier designs are used, then device simplicity is maintained, but saturation power (Psat) cannot reach the required 28 dBm level for 13 GHz band operation
Solution Approach 1:
The biasing circuit is segmented into multiple independent voltage generators (first voltage generator for first bias voltage, second voltage generator for second bias voltage, third voltage generator for third bias voltage) that can be independently optimized and controlled, allowing complex biasing requirements to be met without overwhelming system-level complexity
Solution Approach 2:
The patent introduces a third dimension of control by adding back gate biasing to the conventional front gate biasing, creating a two-gate control system (front gate and back gate) that provides additional degrees of freedom for optimizing transistor performance at high power levels
2Power
If high positive bias voltage is applied to NFET gates to increase power output, then saturation power increases, but reliability specifications are violated due to excessive gate-drain voltage stress
Solution Approach 1:
The negative bias voltage applied to the back gate acts as a counterweight that offsets the high positive voltage stress on the gate-drain junction, allowing the front gate to be driven to high voltages for maximum power output while the back gate simultaneously reduces the net voltage stress to maintain reliability
Solution Approach 2:
By adding the back gate dimension to the control system, the patent creates an additional voltage control path that independently manages the gate-drain voltage stress, separating the power output control (front gate) from the reliability control (back gate) functions
3Reliability
If multiple voltage generators and dual-gate biasing are implemented, then high power operation with improved reliability is achieved, but circuit complexity increases
Solution Approach 1:
The biasing network is divided into three independent voltage generators, each responsible for a specific bias voltage (first, second, and third bias voltages), allowing modular design, independent optimization, and simplified troubleshooting of each segment rather than managing one complex unified biasing system
Solution Approach 2:
The dual-gate transistor structure provides multi-functionality where the front gate handles signal amplification and power output control while the back gate simultaneously manages voltage stress and reliability, making a single transistor structure perform multiple critical functions
Data Source
AI summary
A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.