NFET Gate-Drain Breakdown Simulation Circuit
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Solution Overview
Problem
Existing models fail to accurately simulate the electrical characteristics of N-channel field effect transistors (NFETs) post-gate-to-drain breakdown, leading to underestimated drain current degradation and inadequate modeling of source current effects, particularly at mid-voltage conditions, due to complex terminal coupling and inability to replicate key features of gate-drain breakdown.
Innovation Solution
An equivalent circuit model incorporating a primary FET and two depletion mode FETs connected between the gate and drain, with specific resistor and diode configurations to emulate power law exponent behavior and accurately represent gate, drain, and source currents across a range of voltages, suitable for simulation systems like SPICE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing models are used to simulate NFET post-gate-to-drain breakdown, then the simulation is simple, but the accuracy of electrical characteristics (drain current degradation, source current effects) is insufficient
Solution Approach 1:
The equivalent circuit model is segmented into multiple functional components: a primary FET representing the main channel, first and second depletion mode FETs representing breakdown paths, and associated resistors and diodes. Each component models specific electrical characteristics, allowing accurate representation of complex post-breakdown behavior through modular composition rather than a monolithic inaccurate model.
Solution Approach 2:
Depletion mode FETs are introduced as intermediary elements to model the breakdown path between gate and drain. These intermediary components capture the complex terminal coupling effects and voltage-dependent current characteristics that directly modeling would require excessive complexity, serving as mediators between the primary FET and the external circuit.
2Reliability
If simple breakdown models are used, then the device complexity is low, but the reliability of circuit functionality prediction is reduced
Solution Approach 1:
The equivalent circuit model incorporates dynamic elements including voltage-dependent depletion mode FETs that adjust their conductance based on instantaneous voltage conditions, and resistors that model time-dependent degradation effects. This dynamic behavior allows the model to accurately predict circuit reliability under varying operating conditions rather than relying on static simplifications.
Solution Approach 2:
The model uses parameter changes in the depletion mode FETs to represent different breakdown scenarios and progression stages. By varying parameters such as threshold voltage, transconductance, and resistance values based on breakdown conditions, the model achieves high reliability predictions without requiring a completely different circuit structure for each scenario.
3Measurement precision
If complex terminal coupling is modeled accurately, then the precision of current representation is improved, but the difficulty of model implementation increases
Solution Approach 1:
The depletion mode FETs serve multiple functions simultaneously: they model breakdown current paths, represent terminal coupling effects, capture voltage-dependent behavior, and emulate power law exponent characteristics. This multi-functionality allows accurate current representation without requiring separate dedicated components for each effect, reducing implementation difficulty.
Solution Approach 2:
The equivalent circuit copies the essential electrical behavior of the broken dielectric path using standard semiconductor devices (depletion mode FETs, resistors, diodes) rather than requiring specialized components or complex mathematical models. This copying approach maintains precision while improving implementability through use of conventional circuit elements.
Data Source
AI summary
A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.