NFET Gate Stack With Aluminum-Free Work-Function Layer Reliability

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing the minimum feature size of electronic components, leading to issues such as degradation of gate stack reliability due to the presence of aluminum in work-function layers, which affects the integration density and performance of transistors.

Innovation Solution

The formation of an aluminum-free work-function layer in gate stacks using a metal-containing layer, such as TiN, and a silicon layer, deposited in-situ to reduce the work-function and improve reliability, while avoiding the use of aluminum to prevent degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If aluminum is used in work-function layers, then the work-function can be adjusted for transistor fabrication, but the reliability of the gate stack degrades

Engineering Contradiction:
Improvegate stack reliabilityVSAvoidaluminum-induced degradation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent removes aluminum from the work-function layer composition entirely, extracting the harmful element while maintaining the functional requirements through alternative materials (titanium nitride and tungsten) that do not induce reliability degradation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs composite material structures including titanium nitride/tungsten combinations and titanium nitride/silicon combinations to achieve the desired work-function characteristics without relying on aluminum, thereby eliminating the reliability issues associated with aluminum while maintaining electrical performance

Inventive Principle:
Principle #40Composite materials

2Productivity

If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but gate stack reliability degrades

Engineering Contradiction:
Improveintegration densityVSAvoidgate stack reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By removing aluminum from the work-function layer, the patent eliminates the primary source of reliability degradation that becomes increasingly problematic at smaller feature sizes, enabling continued scaling while maintaining gate stack reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the material composition parameters of the work-function layer, transitioning from aluminum-based materials to aluminum-free materials (titanium nitride and tungsten combinations), which fundamentally alters the electrical and reliability characteristics to support smaller feature sizes

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of gate stacks by reducing the work-function to a desirable range for n-type transistors, improving integration density and performance, and reducing gate resistance by approximately 40% through in-situ deposition methods.

Implementation Method 1

depositing a metal-containing layer; depositing a silicon-containing layer on the metal-containing layer

Methodology Applied
Scientific EffectIn-situ deposition: Physical Vapour Deposition

Data Source

PatentUS20240379777A1NFET with Aluminum-Free Work-Function Layer and Method Forming Same
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379777A1 patent drawing
  • US20240379777A1 patent drawing
  • US20240379777A1 patent drawing

AI summary

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.