NFET Gate Stack With Aluminum-Free Work-Function Layer

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices continue to shrink in size, the integration of electronic components poses challenges, particularly due to the degradation of gate stacks caused by aluminum, which affects the reliability of the resulting semiconductor devices.

Innovation Solution

The formation of an aluminum-free work-function layer in the gate stack, comprising a metal-containing layer and a silicon layer, reduces the work-function and enhances the reliability of the gate stack by eliminating aluminum, which is achieved through in-situ deposition processes to prevent oxidation and ensure nitridation of the silicon layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If aluminum is used in the work-function layer, then the work-function is reduced and device performance is improved, but the reliability of the gate stack degrades

Engineering Contradiction:
Improvegate stack reliabilityVSAvoidaluminum degradation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent removes aluminum from the work-function layer composition entirely, extracting the harmful element while maintaining the necessary electrical functionality through alternative material combinations (titanium nitride and silicon) that do not exhibit the same degradation mechanisms

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention uses a composite structure consisting of titanium nitride and silicon layers to achieve the desired work-function characteristics without aluminum. This composite material approach allows optimization of both reliability and electrical performance by combining materials with complementary properties

Inventive Principle:
Principle #40Composite materials

2Reliability

If in-situ deposition is used, then oxidation is prevented and nitridation is ensured, but process complexity increases

Engineering Contradiction:
Improvegate stack reliabilityVSAvoiddeposition process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple deposition steps (metal layer deposition and silicon layer deposition) into a single in-situ process sequence, eliminating vacuum breaks and environmental exposures that would cause oxidation. This merging of steps prevents contamination while achieving the desired nitridation effect

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The aluminum-free gate stack improves the reliability and reduces gate resistance by up to 40% compared to conventional methods, ensuring consistent performance in advanced semiconductor devices.

Implementation Method 1

depositing a silicon-containing layer on the metal-containing layer... achieved through in-situ deposition processes

Methodology Applied
Scientific EffectIn-situ deposition: Physical Vapour Deposition

Implementation Method 2

ensure nitridation of the silicon layer

Methodology Applied
Scientific EffectNitridation: Nitriding

Data Source

PatentUS12471342B2NFET with aluminum-free work-function layer and method forming same
Publication Date: 2025.11.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12471342B2 patent drawing
  • US12471342B2 patent drawing
  • US12471342B2 patent drawing

AI summary

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.