Selective NFET PFET Recess for Contact Resistance
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Solution Overview
Problem
The formation of Fin Field-Effect Transistors (FinFETs) faces challenges with increasing transistor sizes, leading to higher contact resistance due to smaller source/drain regions, which complicates the manufacturing process.
Innovation Solution
The process involves forming n-type and p-type FinFETs with selective recessing and epitaxial growth of source/drain regions, using specific etching gases and temperature control to optimize etch-back rates and reduce contact resistance, while minimizing etching of p-type regions to preserve electrical conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor sizes are reduced to increase integration density, then device scaling is improved, but contact resistance increases due to smaller source/drain regions
Solution Approach 1:
The patent applies selective recess treatment where only n-type source/drain regions are recessed while p-type regions are protected by polymer layers. This local differentiation allows increased contact area for n-type regions (reducing contact resistance) without affecting p-type regions, thereby resolving the contradiction between device scaling and contact resistance
Solution Approach 2:
The etching process is segmented into selective steps with different polymer protection levels for n-type and p-type regions. This segmentation enables independent optimization of each region's contact properties while maintaining overall device scaling, addressing the contradiction between integration density and contact resistance
2Reliability
If selective recessing is applied to n-type regions to reduce contact resistance, then contact area is increased, but process complexity increases due to selective etching requirements
Solution Approach 1:
The patent employs self-aligned polymer formation where polymers are generated in-situ during etching processes. The polymers automatically protect p-type regions based on their material properties, eliminating the need for separate masking steps and reducing process complexity despite the selective nature of the recessing
Solution Approach 2:
The patent utilizes changes in etching parameters (gas composition, power, pressure) to achieve selective etching rates between n-type and p-type regions. By adjusting these parameters, the process achieves selective recessing without requiring complex additional process steps, thereby managing process complexity while reducing contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and improves device performance by increasing the contact area for n-type FinFETs while maintaining low resistance for p-type FinFETs, thus addressing the manufacturing complexities and performance issues associated with smaller transistor sizes.
Implementation Method 1
conducting a process gas to etch back the first source/drain region and the second source/drain region simultaneously, wherein a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region
Implementation Method 2
adjusting a temperature of a wafer that comprises the first source/drain region and the second source/drain region to lower than about 20° C.
Implementation Method 3
selective recessing and epitaxial growth of source/drain regions
Data Source
AI summary
A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.