N-FET Si1-xGex Source Drain Strain Boosting
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Solution Overview
Problem
Current N-type MOSFETs face challenges with high external resistance and parasitic series source/drain resistance, which affect drive current and drain-induced barrier lowering, making it difficult to achieve high performance and low drain-induced barrier lowering in scaled planar bulk CMOS devices.
Innovation Solution
A method for making an N-FET with a highly doped Si1-xGex source/drain region, where x<0.85, and a Ge channel region, incorporating in-situ doping and tensile strain to reduce parasitic series source/drain resistance and achieve a shallow junction depth, thereby enhancing carrier mobility and drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional N-FET structures are used with shallow source/drain junctions, then device scaling is achieved, but parasitic series source/drain resistance becomes too high
Solution Approach 1:
The patent changes the material composition parameter by using Si1-xGex source/drain regions with controlled germanium content (x<0.85) and implements high-dose in-situ doping to achieve dopant concentrations exceeding 1×10^20 atoms/cm³. These parameter changes reduce the resistivity of the source/drain regions, thereby lowering parasitic series resistance while maintaining shallow junction depths for continued device scaling.
Solution Approach 2:
The patent employs composite material structures including Si1-xGex source/drain regions combined with Ge channel regions, and integrates multiple functional layers such as high-k dielectric gate insulators with metal gate electrodes. This composite approach allows optimization of electrical properties in different regions, achieving low resistance in source/drain while maintaining appropriate band alignment and carrier control in the channel.
2Reliability
If high channel doping is used to reduce parasitic series resistance, then source/drain resistance decreases, but channel length control and junction depth become difficult
Solution Approach 1:
The patent performs preliminary actions by forming the source/drain regions with in-situ doping during the epitaxial growth process before subsequent processing steps. The sacrificial gate spacers are formed and positioned in advance to define the final junction depth, ensuring precise depth control is achieved before high-dose doping is applied, thus preventing dopant diffusion beyond the desired depth.
Solution Approach 2:
The patent introduces sacrificial gate spacers as intermediary structures that temporarily define the source/drain junction depth during fabrication. These spacers act as a mediator between the gate structure and the source/drain regions, allowing precise depth control during doping while being removed later in the process, thus decoupling the depth control function from the final device structure.
3Speed
If Ge MOSFETs are used to improve carrier mobility, then device speed increases, but external resistance and dopant activation become problematic
Solution Approach 1:
The patent applies local quality by using pure Ge material specifically for the channel region where high carrier mobility is required, while using Si1-xGex material for the source/drain regions where low resistance is the priority. This spatial differentiation of material properties allows the device to simultaneously achieve high speed in the channel and low external resistance in the source/drain, resolving the contradiction between these two performance parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a high-speed MOSFET with reduced parasitic series source/drain resistance and improved drive current, along with a shallow source/drain junction depth, effectively addressing the limitations of current N-FET structures.
Implementation Method 1
Tensile strain is induced in the silicon as the lattice of the silicon layer is stretched to mimic the larger lattice constant of the underlying silicon-germanium. Electrons in strained silicon experience less resistance and flow faster than in unstrained silicon
Implementation Method 2
Si1-xGex source/drain regions are doped in-situ during formation
Data Source
AI summary
A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers. Si1-xGex source/drain regions are doped in-situ during formation, x<0.85.