Ni-Sn Chip Stacking With Diffusion Soldering for Low Parasitic Inductance
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Solution Overview
Problem
Existing semiconductor devices with lateral arrangements of transistor and diode components suffer from parasitic inductances that affect switching speed, necessitating alternative interconnect technologies for improved performance.
Innovation Solution
A method involving a substrate with a metallic surface, sequential deposition of Ni and Sn layers, and semiconductor dies on intermetallic compound layers formed by diffusion soldering, creating a vertical chip-to-chip stack to reduce parasitic inductances and enhance switching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If lateral arrangement of transistor and diode components is used, then device assembly is simplified, but parasitic inductances increase and switching speed decreases
Solution Approach 1:
The patent transitions from a lateral (2D) arrangement of transistor and diode components to a vertical (3D) chip-to-chip stacking architecture. This dimensional change allows components to be arranged in multiple layers with direct vertical interconnections, dramatically reducing the length of electrical interconnections and parasitic inductances while maintaining assembly simplicity through standardized stacking processes
2Speed
If vertical chip-to-chip stacking is implemented, then parasitic inductances are reduced and switching speed improves, but interconnect technology complexity increases
Solution Approach 1:
The patent employs composite interconnect structures consisting of multiple material layers including nickel (Ni), nickel phosphide (NiP), and tin (Sn) layers. These composite material stacks provide optimized electrical, mechanical, and diffusion barrier properties that enable reliable vertical interconnections while managing the complexity through material science rather than structural complexity
Solution Approach 2:
The patent utilizes controlled diffusion soldering processes that change the physical and chemical parameters of the intermetallic layers during processing. By controlling temperature, time, and atmospheric conditions, the diffusion process creates optimized intermetallic compound formations that simplify the overall interconnect structure while achieving the required electrical performance
3Reliability
If diffusion soldering process is used, then reliable intermetallic compound layers are formed, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary deposition of specific metal layers (Ni, NiP, Sn) with controlled thicknesses and compositions before the diffusion soldering process. This preliminary preparation ensures that the subsequent diffusion process produces reliable intermetallic compounds with predictable properties, reducing the need for complex process control during the actual diffusion step
Solution Approach 2:
The patent uses intermediate NiP layers as diffusion barriers and transition layers between the Ni and Sn layers. These intermediary layers control the diffusion process, prevent unwanted intermetallic formation, and ensure reliable bonding, thereby simplifying the overall manufacturing process by making the diffusion soldering more predictable and controllable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic inductances and improves switching speed by forming intermetallic compound layers through diffusion soldering, enabling more efficient semiconductor device operation.
Implementation Method 1
performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack
Implementation Method 2
a first intermetallic compound layer disposed on the substrate, the first intermetallic compound layer comprising Ni, Sn and P
Data Source
Figure 1~2
Figure 3~5
AI summary
A method for fabricating a semiconductor device comprises comprising providing a substrate layer stack comprising a substrate with a metallic upper surface, a first Ni containing layer disposed on the substrate, and a first Sn layer on the first Ni containing layer (110); depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die (120); depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprising a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer (130); and performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack (140).