Ni-SnSb Backside Metallization for Thermomechanical Reliability
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Solution Overview
Problem
Semiconductor devices face challenges in balancing electrical and mechanical requirements, such as thermomechanical stress, reliability, and fabrication costs, often leading to competing design choices that compromise performance.
Innovation Solution
The use of a semiconductor device structure comprising a semiconductor die with a Ni comprising layer and a SnSb layer, where the SnSb layer contains 2 wt % to 30 wt % Sb, along with optional additional metal layers and a carrier, to enhance mechanical robustness and reliability while maintaining low thermal resistance and fabrication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer stack is designed to have high reliability vs. thermomechanical stress, then the device reliability improves, but the fabrication complexity and costs increase
Solution Approach 1:
The patent employs a composite metal layer stack comprising multiple layers with distinct functions: a Ni-containing layer (with Si, Cr, or Ti) provides oxidation resistance and mechanical strength, while a SnSb layer (with 2-30 wt% Sb) provides solderability and stress relief. This composite structure achieves high reliability under thermomechanical stress while maintaining manageable fabrication complexity through standardized deposition processes.
2Reliability
If the metal layer stack is designed for high robustness against soldering temperature stress, then the device reliability improves, but the material selection and fabrication complexity increase
Solution Approach 1:
The patent specifies precise compositional parameters to optimize soldering temperature stress resistance: the SnSb layer contains 2-30 wt% Sb, which forms intermetallic compounds with melting points suitable for soldering processes. The Ni-containing layer includes 1-20 at% Si, Cr, or Ti to control oxidation and intermetallic formation during soldering. These parameter specifications enable reliable soldering while maintaining straightforward fabrication through conventional deposition techniques.
3Reliability
If additional metal layers are added to meet electrical and mechanical requirements, then the device performance improves, but the material consumption and fabrication costs increase
Solution Approach 1:
The patent divides the metal layer stack into functionally segmented layers: the Ni-containing layer (50-200 nm thick) specifically addresses oxidation resistance and mechanical strength, while the SnSb layer (1-5 μm thick) specifically addresses solderability and stress relief. This segmentation allows each layer to be optimized for its specific function with minimal thickness, reducing overall material consumption while achieving comprehensive electrical and mechanical performance.
Data Source
AI summary
A semiconductor device includes a semiconductor die including a first side and an opposing second side, a first metallization layer arranged on the first side, a Ni including layer arranged on the second side, wherein the Ni including layer further includes one or more of Si, Cr and Ti, and a SnSb layer arranged on the Ni comprising layer, wherein an amount of Sb in the SnSb layer is in the range of 2 wt % to 30 wt %.