NIC-Based Address Translation for High-Rate Inter-Process Messaging
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Solution Overview
Problem
Existing network address translation methods in software incur performance penalties due to cache misses and security risks, especially in high-performance computing environments with large numbers of endpoints and high message rates, diverting CPU resources and posing security threats.
Innovation Solution
Implementing network address translation in hardware, specifically through a network interface controller (NIC), using a multi-part translation process that combines table lookup with a translation algorithm to efficiently translate logical network addresses, reducing the size of translation tables and minimizing CPU burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If network address translation is implemented in software, then it can be flexibly configured and updated, but it incurs performance penalties due to cache misses and diverts CPU resources
Solution Approach 1:
The patent segments the network address translation functionality into two parts: a compressed translation table stored in limited on-chip memory and a decompression circuit that expands entries on-demand. This segmentation allows the system to maintain a large logical translation table while using minimal physical memory resources, resolving the contradiction between configuration flexibility and processing throughput.
Solution Approach 2:
The patent transitions from a traditional software-based NAT implementation to a hardware-based implementation using a network interface controller with dedicated decompression circuitry. This dimensional change from software to hardware enables simultaneous configuration flexibility and high message processing throughput by performing translation operations in parallel with message handling.
2Quantity of substance
If large translation tables are used to support many endpoints, then address coverage is sufficient, but cache misses increase and performance degrades
Solution Approach 1:
The patent implements a nested structure where a compressed translation table is stored within limited on-chip memory resources, and a decompression circuit nested within the network interface controller expands table entries on-demand. This nested architecture enables support for many endpoints while maintaining fast access times and avoiding cache misses.
Solution Approach 2:
The patent changes the physical state of the translation table from a fully expanded form in memory to a compressed form in on-chip storage, with dynamic decompression of individual entries. This parameter change in data representation allows the system to support a large number of endpoints while using minimal memory resources and maintaining high processing speed.
3Speed
If translation tables are stored in on-chip memory, then access speed increases, but the size of tables that can be supported is limited
Solution Approach 1:
The patent performs preliminary compression of the translation table and stores the compressed form in on-chip memory. When translation is needed, the decompression circuit rapidly expands the required entries on-demand. This preliminary compression action enables the system to maintain both fast access speed and large table capacity by preparing the data in a space-efficient format while providing rapid expansion when needed.
Data Source
AI summary
In certain implementations, a method includes receiving, by a network interface controller (NIC), a request for inter-process communication associated with a sending process of a distributed application. The request includes a logical network address for a destination process of the distributed application. The method includes executing, by the NIC, a network address translation process to translate the logical network address for the destination process to a translated network address for the destination process. The network address translation process includes executing, using a first portion of the logical network address, a lookup of a network address translation table to determine a first address; determining a translation modifier by executing a translation algorithm using a second portion of the logical network address; and determining the translated network address using the first address and the translation modifier. The method includes processing, by the NIC, a first message using the translated network address.