Network Interface Card with Cache Mirror Registers for Parallel Computing
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Solution Overview
Problem
Current operating systems for cluster computers are designed for networks with large latency, making them inefficient for handling short packets, which leads to suboptimal performance and increased latency in data transfer between processing nodes.
Innovation Solution
A novel network interface card (NIC) with cache mirror registers and a controller that manages data flow without interrupting processors, using Data Vortex switches to efficiently handle short packets and reduce latency by directly transferring data to processors' local memory, cache, or working registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current operating systems designed for large latency networks are used, then compatibility with existing network infrastructure is maintained, but data transfer efficiency and performance for short packets deteriorate
Solution Approach 1:
The network interface card is segmented into multiple cache mirror registers that can independently hold and manage data packets. This segmentation allows short packets to be stored and forwarded without requiring processor intervention for each individual packet, thereby reducing latency and improving data transfer efficiency while maintaining compatibility with existing network infrastructure.
Solution Approach 2:
Cache mirror registers serve as an intermediary buffer between the network and the processor. These registers temporarily store incoming data packets, allowing the network interface to operate independently from the processor. This intermediary mechanism eliminates the need for processor interrupts for each packet, reducing latency and improving overall system performance while maintaining compatibility with current operating systems.
2Productivity
If processors are interrupted for each data transfer request, then data accuracy and control are maintained, but processing speed and system performance deteriorate
Solution Approach 1:
The cache mirror registers are designed to autonomously manage data transfer operations without requiring processor intervention. The registers can independently receive, store, and forward data packets based on predefined conditions, enabling the system to maintain reliable data transfer control while significantly improving processing speed by eliminating frequent processor interrupts.
3Loss of time
If traditional network interface cards are used without cache mirror registers, then device simplicity is maintained, but data transfer latency and processor overhead increase
Solution Approach 1:
The cache mirror registers are designed with multi-functionality, serving as both data storage buffers and intelligent forwarding agents. These registers can handle multiple types of data packets, support different transfer modes, and interact with various processor architectures, making the enhanced network interface universally applicable while effectively reducing data transfer latency without proportionally increasing device complexity.
Data Source
AI summary
A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.