NIC DCA Control Settings for Packet Portion Caching

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Solution Overview

Problem

Existing direct cache access (DCA) systems are inefficient due to suboptimal data transfer into the CPU cache, leading to cache misses and memory access penalties, as they do not account for protocol and application-specific requirements, resulting in performance bottlenecks.

Innovation Solution

Implementing a network interface controller (NIC) that defines DCA control settings for each I/O device queue to selectively copy relevant packet portions to the CPU cache based on packet analysis, protocol, and application requirements, thereby optimizing cache usage and reducing cache misses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred into CPU cache using existing DCA systems, then cache access speed is improved, but cache miss rate increases due to suboptimal data transfer

Engineering Contradiction:
Improvecache access speedVSAvoidcache hit rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the data transfer process by dividing packets into different portions (e.g., header, payload) and selectively caching only specific portions based on protocol type and application requirements. This is achieved through packet parsing that identifies boundaries of portions and DCA control settings that specify which portions to copy to cache, thereby optimizing cache content and reducing cache misses while maintaining fast access speed.

Inventive Principle:
Principle #1Segmentation

2Reliability

If more data is transferred into CPU cache, then cache hit rate may improve, but cache eviction of relevant data occurs causing performance degradation

Engineering Contradiction:
Improvecache hit rateVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by making different parts of the cache serve different purposes based on protocol and application requirements. Through DCA control settings specific to each I/O device queue and packet portion, the system ensures that only locally relevant data (specific packet portions needed by particular applications) is cached, optimizing both hit rate and overall system performance by preventing unnecessary evictions.

Inventive Principle:
Principle #3Local quality

3Productivity

If protocol and application-specific DCA control is implemented, then data transfer optimization is achieved, but device complexity increases

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidNIC configuration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamics by making the DCA control settings configurable and adaptable to different protocols and applications. The NIC can dynamically adjust which packet portions are cached based on the specific protocol type and application requirements, allowing the system to optimize data transfer efficiency for each scenario while managing complexity through flexible, context-aware control mechanisms.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9985977B2Direct cache access for network input/output devices
Publication Date: 2018.05.29 FORTINET INC
  • US9985977B2 patent drawing
  • US9985977B2 patent drawing
  • US9985977B2 patent drawing

AI summary

Methods and systems for improving efficiency of direct cache access (DCA) are provided. According to one embodiment, a set of DCA control settings are defined by a network interface controller (NIC) of a network security device for each of multiple I/O device queues. The control settings specify portions of network packets that are to be copied to a cache of the corresponding CPU. A packet is received by the NIC. The packet is parsed to identify boundaries of portions of the packet and is queued onto an I/O device queue. The packet is then transferred from the I/O device queue to a host memory of the network security device and the specified portions are concurrently copied to the cache of the corresponding CPU based on the control setting associated with the I/O device queue.