Network Interface Controller Dynamic Packet Flow Routing

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Solution Overview

Problem

Increased network traffic and connection speeds put a significant burden on host processor resources due to frequent memory accesses for TCP control block data, which can degrade system performance, especially in multi-processor systems where maintaining cache consistency is challenging.

Innovation Solution

Implementing a network interface controller that learns to direct packets by identifying sources of egress packets and updating its flow mapping, allowing it to route ingress packets efficiently without explicit configuration messages, thereby reducing runtime configuration and adapting quickly to changes in processor and queue assignments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TCP operations are handled by host processors, then connection management and data transfer reliability are maintained, but processor resources are heavily burdened by frequent memory accesses for TCP control block data

Engineering Contradiction:
Improveconnection managementVSAvoidprocessor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts TCP control block data from main memory and places it in processor-specific cache memory. This extraction reduces the burden on host processors by minimizing frequent memory accesses, thereby improving processor performance while maintaining connection management reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system performs preliminary actions by pre-loading TCP control block data into cache memory before it is needed for packet processing. This preliminary caching action reduces latency during packet handling and improves overall processor productivity without compromising connection management.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If TCP control block data is cached in processor-specific cache memory, then memory access frequency is reduced and processor performance improves, but cache consistency becomes difficult to maintain in multi-processor systems

Engineering Contradiction:
Improveprocessor performanceVSAvoidcache consistency
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent segments TCP control block data by associating each processor with its own dedicated cache memory for storing TCP control blocks. This segmentation allows each processor to independently manage its cache without consistency conflicts, maintaining both processor performance and cache stability in multi-processor systems.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each processor has local access to its own cached TCP control block data, providing local quality optimization. This local caching strategy eliminates the need for inter-processor cache synchronization, thereby maintaining cache consistency while improving processor performance.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If explicit configuration messages are used to direct packet flows to processors, then packet routing is controlled, but runtime configuration overhead and bus traffic increase

Engineering Contradiction:
Improvepacket routing controlVSAvoidconfiguration time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The network interface controller performs self-service by autonomously learning and adapting packet flow routing based on observed packet patterns. This eliminates the need for explicit configuration messages, reducing runtime configuration overhead and bus traffic while maintaining ease of packet routing control.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements feedback mechanisms where the network interface controller monitors packet flows and automatically adjusts routing decisions based on observed patterns. This feedback-driven adaptive routing eliminates configuration messages and reduces setup time while maintaining routing control.

Inventive Principle:
Principle #23Feedback

4Adaptability or versatility

If packet flows are dynamically assigned to processors based on learned patterns, then adaptation to processor and queue assignments is immediate, but the complexity of flow mapping management increases

Engineering Contradiction:
Improveadaptation speedVSAvoidflow mapping complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic flow mapping where the network interface controller continuously learns and adapts packet flow routing based on observed patterns and system state. This dynamic adaptation enables immediate response to processor and queue assignments while the learning algorithms manage the complexity of flow mapping automatically.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7620046B2Dynamically assigning packet flows
Publication Date: 2009.11.17 INTEL CORP
  • US7620046B2 patent drawing
  • US7620046B2 patent drawing
  • US7620046B2 patent drawing

AI summary

In general, in one aspect, the disclosure describes a method includes accessing data of an egress packet belonging to a flow, storing data associating the flow with at least one queue based on a source of the data of the egress packet. The method also includes accessing an ingress packet belonging to the flow, performing a lookup of the at least one queue associated with the flow, and enqueueing data of the ingress packet to the at least one queue associated with the flow.