NIC Packet Flow Analytics for Queue Steering and Core Tuning

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Solution Overview

Problem

Existing computer systems face inefficiencies in processing network packets due to inadequate prioritization and frequency tuning of processor cores, leading to suboptimal power consumption and performance.

Innovation Solution

Implementing a system that utilizes network interface controllers (NICs) to perform packet flow analytics, steering packets into priority queues based on per-flow analytics information and adjusting core frequencies accordingly to optimize processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all packets are processed by all processor cores at high frequency, then processing capacity is maximized, but power consumption increases significantly

Engineering Contradiction:
Improvepacket processing capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments packet flows into different priority queues based on per-flow analytics information. High-priority packets are separated from low-priority packets, allowing selective processing at different frequencies. This segmentation enables the system to process only necessary packets at high frequency, reducing overall power consumption while maintaining processing capacity for critical traffic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic frequency adjustment of processor cores based on real-time packet flow characteristics. Processor cores can transition between different frequency states (high, medium, low) depending on the priority and characteristics of packets being processed. This dynamic adaptation allows the system to optimize power consumption by operating at lower frequencies when high processing capacity is not required.

Inventive Principle:
Principle #15Dynamics

2Speed

If processor cores operate at high frequency continuously, then processing speed is maximized, but power consumption increases

Engineering Contradiction:
Improvepacket processing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic frequency adjustment based on packet flow characteristics. Processor cores operate at high frequency only during periods when high-priority packets are detected, and transition to lower frequencies during periods with only low-priority traffic. This periodic adaptation of processing speed to actual workload requirements reduces power consumption while maintaining processing speed when needed.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the operating frequency parameter of processor cores dynamically based on per-flow analytics information. The system monitors packet characteristics and adjusts the frequency parameter accordingly, switching between high, medium, and low frequency states. This parameter adjustment allows the system to optimize the trade-off between processing speed and power consumption in real-time.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If packets are processed in a first-come-first-served manner, then processing is simple, but high-priority packets may experience delays

Engineering Contradiction:
Improveprocessing simplicityVSAvoidpacket delivery priority
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent segments incoming packet flows into multiple priority queues (high-priority and low-priority queues) based on per-flow analytics information. This segmentation allows the system to apply different processing policies to different packet types. High-priority packets are placed in dedicated queues that are serviced preferentially, ensuring their timely delivery while maintaining relatively simple processing logic through clear queue separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces priority queues as intermediary structures between packet reception and processing. These queues act as mediators that buffer and organize packets according to priority before they are handed off to processor cores. This intermediary mechanism simplifies the processing logic by providing a clear queue-based discipline while ensuring that high-priority packets are handled with appropriate urgency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12457178B2NIC priority queue steering and processor unit frequency tuning based on packet flow analytics
Publication Date: 2025.10.28 INTEL CORP
  • US12457178B2 patent drawing
  • US12457178B2 patent drawing
  • US12457178B2 patent drawing

AI summary

In one embodiment, a system comprises a network interface controller comprising circuitry to determine per-flow analytics information for a plurality of packet flows that are received at the network interface controller and to facilitate differential rate processing of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information.