Network Interface Card Frame Distribution Circuit
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Solution Overview
Problem
High-speed Ethernet network interface cards require substantial computing resources to decode headers, calculate error checking signatures, and route packets efficiently, leading to host processor overload and the need for obsolete hardware updates as standards and protocols evolve.
Innovation Solution
A multi-core processor-based network interface card with a programmable distribution circuit that uses hash functions and masks to efficiently direct frames to appropriate processor cores based on protocol-specific parameters, allowing for real-time optimal frame distribution and adaptation to changing protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a network interface card processes high-speed Ethernet frames (40 Gbits/s), then the processing speed and throughput are improved, but the computing resources required for decoding headers, calculating error checking signatures, and routing packets increase substantially, leading to host processor overload
Solution Approach 1:
The patent divides the network interface card into multiple independent processing cores, each capable of handling specific frames. This segmentation allows parallel processing of multiple frames simultaneously, distributing the computational load across cores rather than overwhelming a single processor, thus maintaining high processing speed while managing resource requirements through parallelization
Solution Approach 2:
The patent implements a distribution circuit that performs preliminary actions by analyzing frame headers and calculating distribution indices before frames reach the processing cores. This pre-processing includes extracting relevant parameters from headers, applying hash functions, and determining target core assignments in advance, which reduces the computational burden on the host processor during actual frame processing
2Productivity
If the network interface card uses fixed hardware architecture to process Ethernet frames, then processing efficiency is improved, but the system becomes obsolete as standards and protocols evolve, requiring hardware updates
Solution Approach 1:
The patent implements a programmable distribution circuit that can be reconfigured through firmware updates to handle new protocols and standards. The distribution rules and hash functions are stored in programmable memory, allowing the system to dynamically adapt its processing logic without hardware changes, maintaining processing efficiency while gaining versatility across evolving Ethernet standards
Solution Approach 2:
The patent creates a universal processing architecture where multiple cores can handle various frame types and protocols through a common distribution mechanism. The distribution circuit is designed to work with different Ethernet standards (including 40 Gbits/s and future speeds) by programmatically adjusting distribution rules, making the system multi-functional and future-proof without requiring dedicated hardware for each protocol version
3Productivity
If multiple processing cores are used to handle frames in parallel, then processing capacity is improved, but ensuring optimal distribution of frames to appropriate cores based on protocol-specific parameters becomes more complex
Solution Approach 1:
The patent introduces a distribution circuit as an intermediary between the incoming frames and the processing cores. This intermediary performs the complex task of analyzing frame headers, extracting protocol-specific parameters, applying hash functions, and determining target core assignments. By centralizing this distribution logic in a dedicated circuit rather than distributing it across all cores, the system achieves parallel processing capacity while managing distribution complexity in a single location
Data Source
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Figure 6A~8
AI summary
The invention relates to a method for processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions, positions at which are expected, in a frame, at least one parameter characterizing a subframe (12) and parameters (24, 26, 30, 37, 39) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame (ETHin) and comparing the value received at position (12) of the subframe parameter to the expected value; in case of equality, calculating an index (IDX) from the values received at the positions of the session parameters; and directing the current frame to a processing resource (C1, C2...) associated with the index.