NIC Header Modification Engine Offloads Packet Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional methods for implementing header modification functions in network routers or switches require large memory storage and complex logic, leading to limitations in cost and scalability, while CPU-based solutions are inefficient for high-speed packet processing.

Innovation Solution

Implementing header modification functions in a Network Interface Controller (NIC) that uses existing interface logic and direct memory access (DMA) capabilities to store header modification tables, allowing for efficient modification of packet headers and offloading network protocols to the NIC.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If header modification functions are implemented in network routers or switches, then header processing capability is improved, but device complexity and cost increase due to large memory storage and complex logic requirements

Engineering Contradiction:
Improveheader processing capabilityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the header modification function from traditional network routers or switches and relocates it to the NIC. This is achieved by implementing a header modification engine within the NIC that can parse packet headers, lookup modification rules from tables stored in host memory, and perform header modifications without requiring complex logic in the network device itself.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces the NIC as an intermediary component between the host computer and the network. The NIC acts as a mediator that handles header modification operations by leveraging the host memory for rule storage and its own processing capabilities for execution, thereby avoiding the need for complex logic in routers or switches.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If header modification functions are implemented in CPU-based solutions, then flexibility and control are improved, but processing speed decreases due to CPU overhead

Engineering Contradiction:
ImproveflexibilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the packet processing function by separating header modification from the main CPU processing workload. The NIC's header modification engine handles header parsing and modification independently using dedicated hardware logic and lookup tables, while the CPU focuses on higher-level protocol processing and application logic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables the NIC to perform header modification operations autonomously without requiring CPU intervention for each packet. The header modification engine uses pre-configured lookup tables stored in host memory to automatically determine and execute the appropriate header modifications, making the system self-sufficient for this specific function.

Inventive Principle:
Principle #25Self-service

3Productivity

If large memory storage is used in routers or switches for header modification tables, then processing capability is improved, but cost and scalability are worsened

Engineering Contradiction:
Improveprocessing capabilityVSAvoidmemory storage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent makes the host memory serve multiple functions: it stores the operating system, application data, and header modification rule tables. This multi-functional use of existing memory resources eliminates the need for dedicated large memory storage in routers or switches, reducing overall system cost while maintaining processing capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20220377014A1Generic Packet Header Insertion and Removal
Publication Date: 2022.11.24 MELLANOX TECHNOLOGIES LTD(IL)
  • US20220377014A1 patent drawing
  • US20220377014A1 patent drawing
  • US20220377014A1 patent drawing

AI summary

A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.