NIC Host Interface SMP Scheduling for Multi-Protocol Packet Processing

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Solution Overview

Problem

Existing network interface controllers (NICs) often lack support for various software interface languages, leading to compatibility issues based on vendor and model, which hinders efficient data transmission and processing in packet-switched networks.

Innovation Solution

Implementing a flexible host interface with a symmetric multi-processing (SMP) array in the hardware data path to dynamically support multiple protocols and drivers, enabling seamless communication between host software and NIC hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a traditional NIC interface is used, then the device complexity is reduced, but the adaptability to different software interface languages and protocols deteriorates

Engineering Contradiction:

Improveprotocol compatibilityVSAvoidinterface structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The host interface is designed with a configurable message processor array that can be dynamically configured to support multiple software interface languages and protocols. This universal design allows a single interface structure to perform multiple protocol-handling functions, improving adaptability without proportionally increasing device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The message processor array employs dynamic configuration capabilities where processing elements can be reconfigured at runtime to match the required protocol or interface language. This dynamic adaptability allows the interface to transform its behavior based on communication requirements, resolving the contradiction between fixed structure and variable protocol support.

Inventive Principle:

Principle #15Dynamics

2Productivity

If a flexible host interface with SMP array is implemented, then the productivity of network packet processing is improved, but the device complexity increases

Engineering Contradiction:

Improvepacket processing efficiencyVSAvoidhost interface structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The host interface is segmented into multiple independent message processor elements within the SMP array, each capable of handling specific protocol tasks. This segmentation allows parallel processing of network packets, improving productivity while keeping individual element complexity manageable through modular design.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The message processor array includes self-configuration capabilities where processing elements can automatically allocate and optimize their own resources based on the protocol requirements. This self-service mechanism reduces the need for complex external control logic, improving productivity without proportionally increasing overall device complexity.

Inventive Principle:

Principle #25Self-service

3Adaptability or versatility

If vendor-specific interface languages are used, then the ease of manufacture is improved, but the adaptability to different NIC models and vendors deteriorates

Engineering Contradiction:

Improvevendor compatibilityVSAvoidinterface implementation

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The host interface uses configurable parameters that can be adjusted to match different vendor-specific protocols and interface languages. By changing operational parameters rather than physical structure, the system achieves vendor compatibility while maintaining a standardized manufacturing process, thus improving adaptability without compromising ease of manufacture.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250373712A1Technologies for managing a flexible host interface of a network interface controller

Publication Date: 2025.12.04 INTEL CORP

AI summary

Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.