NIC Flexible Memory Handling via Indirect Keys

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Solution Overview

Problem

Current I/O devices do not support dynamic memory allocation for network input/output operations, limiting programmers to statically-allocated memory, which restricts flexible and efficient use of memory resources.

Innovation Solution

An I/O device with processing circuitry that translates virtual addresses into physical addresses using memory keys, including indirect memory keys that point to multiple direct memory keys, allowing for dynamic registration and access of non-contiguous memory ranges, enabling application-level dynamic memory registration and supporting virtual memory addressing coordinated with host memory management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If static memory allocation is used for network I/O operations, then memory access is simple and reliable, but memory resource utilization is inefficient and flexible

Engineering Contradiction:
Improvememory resource flexibilityVSAvoidmemory management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic memory allocation mechanisms where the I/O device can register and unregister memory regions at runtime based on actual I/O needs. The processing circuitry dynamically translates virtual addresses to physical addresses using memory keys, enabling flexible memory management that adapts to varying workloads while maintaining efficient resource utilization.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces memory keys as intermediary structures that mediate between virtual address spaces and physical memory. These keys enable the I/O device to translate addresses without requiring direct knowledge of the host memory layout, simplifying the interface while enabling flexible memory registration and access patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If virtual memory addressing is implemented for I/O operations, then memory space utilization is improved, but address translation complexity increases

Engineering Contradiction:
Improveaddressable memory spaceVSAvoidaddress translation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent uses memory keys as copies or references to actual memory regions. Instead of directly managing complex virtual-to-physical address translations, the system uses these key structures that point to memory regions, simplifying the translation process while enabling extended address spaces through the key-based abstraction layer.

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If indirect memory keys pointing to multiple direct memory keys are used, then non-contiguous memory ranges can be accessed, but processing complexity increases

Engineering Contradiction:
Improvememory range accessibilityVSAvoidI/O operation processing speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments memory access into discrete key-based units. Indirect memory keys point to multiple direct memory keys, each representing a specific memory segment. This segmentation allows the I/O device to access non-contiguous memory ranges by processing individual key references, maintaining efficiency through structured memory organization while enabling flexible access patterns.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8645663B2Network interface controller with flexible memory handling
Publication Date: 2014.02.04 MELLANOX TECHNOLOGIES LTD(IL)
  • US8645663B2 patent drawing
  • US8645663B2 patent drawing
  • US8645663B2 patent drawing

AI summary

An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.